Anthony Gutierrez 0ac4624595 arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2 ... the Cortex-A15 has a random replacement policy for its L2 cache. see the Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.		2014-07-28 12:22:00 -04:00
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boot	rcs scripts: remove bbench.rcS	2013-04-02 12:46:49 -04:00
common	arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2	2014-07-28 12:22:00 -04:00
dram	config: Bump DRAM sweep bus speed to match DDR4 config	2014-05-09 18:58:49 -04:00
example	configs: use SimpleMemory when using ruby in se mode	2014-04-01 11:17:46 -05:00
ruby	config: ruby: remove memory controller from network test	2014-04-19 09:00:30 -05:00
splash2	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
topologies	config: topologies: slight code refactor	2014-02-23 19:16:15 -06:00