arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2
the Cortex-A15 has a random replacement policy for its L2 cache. see the Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.
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@ -189,4 +189,4 @@ class O3_ARM_v7aL2(BaseCache):
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prefetch_on_access = 'true'
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# Simple stride prefetcher
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prefetcher = StridePrefetcher(degree=8, latency = 1)
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tags = RandomRepl()
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