sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2

Browse source 
the Cortex-A15 has a random replacement policy for its L2 cache. see the
Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this
patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.
This commit is contained in:
Anthony Gutierrez 2014-07-28 12:22:00 -04:00
parent cbf417c713
commit 0ac4624595
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
configs/common/O3_ARM_v7a.py
View file

@ -189,4 +189,4 @@ class O3_ARM_v7aL2(BaseCache):
prefetch_on_access = 'true'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
tags = RandomRepl()