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arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2

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the Cortex-A15 has a random replacement policy for its L2 cache. see the
Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this
patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.
This commit is contained in:
Anthony Gutierrez 2014-07-28 12:22:00 -04:00
parent cbf417c713
commit 0ac4624595
1 changed files with 1 additions and 1 deletions
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configs/common/O3_ARM_v7a.py
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@ -189,4 +189,4 @@ class O3_ARM_v7aL2(BaseCache):
prefetch_on_access = 'true'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
tags = RandomRepl()