Dam Sunwoo 2c1e344313 cpu: generate SimPoint basic block vector profiles ... This patch is based on http://reviews.m5sim.org/r/1474/ originally written by Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout folder) based on start and end addresses of basic blocks. Some comments to the original patch are addressed and hooks are added to create and resume from checkpoints based on instruction counts dictated by external SimPoint analysis tools. SimPoint creation/resuming options will be implemented as a separate patch.		2013-04-22 13:20:31 -04:00
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arch	sim: Add helper functions that add PCEvents with custom arguments	2013-04-22 13:20:31 -04:00
base	base: load weak symbols from object file	2013-04-17 16:07:19 -05:00
cpu	cpu: generate SimPoint basic block vector profiles	2013-04-22 13:20:31 -04:00
dev	ARM: Add support for HDLCD controller for TC2 and newer Versatile Express tiles.	2013-04-22 13:20:31 -04:00
doc	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	scons: Add warning for missing declarations	2013-02-19 05:56:07 -05:00
mem	ruby: moesi cmp directory: add copyright notice	2013-04-17 16:06:58 -05:00
proto	mem: Add a generic id field to the packet trace	2013-03-26 14:46:45 -04:00
python	scons: Add warning for missing declarations	2013-02-19 05:56:07 -05:00
sim	sim: Add helper functions that add PCEvents with custom arguments	2013-04-22 13:20:31 -04:00
unittest	AddrRange: Transition from Range<T> to AddrRange	2012-09-19 06:15:44 -04:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	scons: don't die on warnings in swig-generated code	2013-03-27 10:03:02 -07:00