gem5/src/arch
Kevin Lim e7ccc94ea3 Various serialization changes to make it possible for the O3CPU to checkpoint.
src/arch/alpha/regfile.hh:
    Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
    Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Push common serialization code to ThreadState level.  Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
    Move common serialization code into ThreadState.

--HG--
extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
2006-07-06 17:53:26 -04:00
..
alpha Various serialization changes to make it possible for the O3CPU to checkpoint. 2006-07-06 17:53:26 -04:00
mips more steps toward O3 SMT 2006-07-06 11:25:44 -04:00
sparc add syscall emulation page table fault so we can allocate more stack pages 2006-06-26 16:49:05 -04:00
isa_parser.py Merging in a month of changes 2006-06-09 03:57:25 -04:00
isa_specific.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
SConscript Fix up code to be able to use the Checker. 2006-06-17 22:01:30 -04:00