725 lines
82 KiB
Plaintext
725 lines
82 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.041682 # Number of seconds simulated
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sim_ticks 41681685000 # Number of ticks simulated
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final_tick 41681685000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 117228 # Simulator instruction rate (inst/s)
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host_op_rate 117228 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 53167547 # Simulator tick rate (ticks/s)
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host_mem_usage 270132 # Number of bytes of host memory used
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host_seconds 783.97 # Real time elapsed on the host
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sim_insts 91903056 # Number of instructions simulated
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sim_ops 91903056 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
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system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 4290038 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3291997 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 7582035 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 4290038 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 4290038 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 4290038 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3291997 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 7582035 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 4938 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 443 # Per bank write bursts
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system.physmem.perBankRdBursts::1 270 # Per bank write bursts
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system.physmem.perBankRdBursts::2 295 # Per bank write bursts
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system.physmem.perBankRdBursts::3 499 # Per bank write bursts
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system.physmem.perBankRdBursts::4 209 # Per bank write bursts
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system.physmem.perBankRdBursts::5 212 # Per bank write bursts
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system.physmem.perBankRdBursts::6 207 # Per bank write bursts
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system.physmem.perBankRdBursts::7 265 # Per bank write bursts
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system.physmem.perBankRdBursts::8 219 # Per bank write bursts
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system.physmem.perBankRdBursts::9 249 # Per bank write bursts
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system.physmem.perBankRdBursts::10 238 # Per bank write bursts
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system.physmem.perBankRdBursts::11 236 # Per bank write bursts
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system.physmem.perBankRdBursts::12 379 # Per bank write bursts
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system.physmem.perBankRdBursts::13 325 # Per bank write bursts
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system.physmem.perBankRdBursts::14 469 # Per bank write bursts
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system.physmem.perBankRdBursts::15 423 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 41681611000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 4938 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1049 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 74 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 856 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 367.551402 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 223.659981 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 343.121338 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 258 30.14% 30.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 183 21.38% 51.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 95 11.10% 62.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 63 7.36% 69.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 46 5.37% 75.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 30 3.50% 78.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 51 5.96% 84.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 22 2.57% 87.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 108 12.62% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 856 # Bytes accessed per row activation
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system.physmem.totQLat 35422000 # Total ticks spent queuing
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system.physmem.totMemAccLat 128009500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 7173.35 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 25923.35 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.06 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 4077 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 8440990.48 # Average gap between requests
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system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 39211333500 # Time in different power states
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system.physmem.memoryStateTime::REF 1391780000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 1076956500 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.throughput 7582035 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 3216 # Transaction distribution
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system.membus.trans_dist::ReadResp 3216 # Transaction distribution
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system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
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system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9876 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 9876 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 316032 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 316032 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 5782000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 45945000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 13412628 # Number of BP lookups
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system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 3768498 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 50.757737 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 19996260 # DTB read hits
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system.cpu.dtb.read_misses 10 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 19996270 # DTB read accesses
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system.cpu.dtb.write_hits 6501862 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 6501885 # DTB write accesses
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system.cpu.dtb.data_hits 26498122 # DTB hits
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system.cpu.dtb.data_misses 33 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 26498155 # DTB accesses
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system.cpu.itb.fetch_hits 9956951 # ITB hits
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system.cpu.itb.fetch_misses 49 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 9957000 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
|
system.cpu.numCycles 83363371 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.branch_predictor.predictedTaken 5905663 # Number of Branches Predicted As Taken (True).
|
|
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
|
|
system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File
|
|
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
|
system.cpu.regfile_manager.intRegFileAccesses 136146025 # Total Accesses (Read+Write) to the Int. Register File
|
|
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
|
|
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
|
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
|
|
system.cpu.regfile_manager.regForwards 38521865 # Number of Registers Read Through Forwarding Logic
|
|
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
|
|
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
|
|
system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed.
|
|
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
|
system.cpu.threadCycles 82970271 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 10393 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 7755613 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 75607758 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 90.696618 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
|
system.cpu.comStores 6501103 # Number of Store instructions committed
|
|
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
|
system.cpu.comNops 7723346 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 43665352 # Number of Integer instructions committed
|
|
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 0.907079 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 0.907079 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.102439 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 1.102439 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 27683021 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 55680350 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 66.792345 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 34111687 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 59.080725 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 33512024 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 59.800061 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 65336871 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 18026500 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 21.624006 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 29503616 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 64.608418 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.tags.replacements 7635 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1492.194030 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.194030 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.728610 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.728610 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 959 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 19923422 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 19923422 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 9945551 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 11400 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 11400 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 11400 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 11400 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 11400 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 11400 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327908250 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 327908250 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 327908250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 327908250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 327908250 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 327908250 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 9956951 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 9956951 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 9956951 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 9956951 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 9956951 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 9956951 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28763.881579 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 28763.881579 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 28763.881579 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 28763.881579 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1880 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1880 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1880 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1880 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1880 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1880 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268503000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 268503000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268503000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 268503000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268503000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 268503000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28204.096639 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28204.096639 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 18195042 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19040 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 23593 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609280 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 758400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 14805000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3522500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 2189.603987 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 17.844250 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.772066 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 350.987671 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3282 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 168 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2213 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.100159 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 99830 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 99830 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 6805 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191445500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31242750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 222688250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 121662250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 121662250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 191445500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 152905000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 344350500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 191445500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 152905000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 344350500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68520.221904 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74034.952607 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69243.858831 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70651.713124 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70651.713124 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69734.811665 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69734.811665 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156316500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25982750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 182299250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100579250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100579250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156316500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 126562000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 282878500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156316500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 126562000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 282878500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55947.208304 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61570.497630 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56685.090174 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58408.391405 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58408.391405 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 157 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 1441.383569 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 26488452 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 11915.632928 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.383569 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 403 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 19995619 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 19995619 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 6492833 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 6492833 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 26488452 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 26488452 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 26488452 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 26488452 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 579 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 579 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 8270 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 8270 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 8849 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 8849 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 8849 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 8849 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39903000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 39903000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 493053000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 493053000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 532956000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 532956000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 532956000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 532956000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001272 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001272 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68917.098446 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 68917.098446 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59619.467956 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 59619.467956 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 60227.822353 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 60227.822353 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 836 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.770335 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6522 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 6522 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 6626 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 6626 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 6626 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 6626 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32266250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32266250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 123679750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 123679750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155946000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 155946000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155946000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 155946000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67928.947368 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67928.947368 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70755.005721 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70755.005721 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|