29e8bcead5
When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
172 lines
5.1 KiB
C++
172 lines
5.1 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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* Jaidev Patwardhan
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*/
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#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
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#define __ARCH_MIPS_ISA_TRAITS_HH__
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#include "arch/mips/types.hh"
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#include "arch/mips/mips_core_specific.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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namespace LittleEndianGuest {};
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class StaticInstPtr;
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namespace MipsISA
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{
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using namespace LittleEndianGuest;
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StaticInstPtr decodeInst(ExtMachInst);
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// MIPS DOES have a delay slot
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#define ISA_HAS_DELAY_SLOT 1
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const Addr PageShift = 13;
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const Addr PageBytes = ULL(1) << PageShift;
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const Addr Page_Mask = ~(PageBytes - 1);
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const Addr PageOffset = PageBytes - 1;
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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const Addr PteShift = 3;
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const Addr NPtePageShift = PageShift - PteShift;
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const Addr NPtePage = ULL(1) << NPtePageShift;
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const Addr PteMask = NPtePage - 1;
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//// All 'Mapped' segments go through the TLB
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//// All other segments are translated by dropping the MSB, to give
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//// the corresponding physical address
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// User Segment - Mapped
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const Addr USegBase = ULL(0x0);
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const Addr USegEnd = ULL(0x7FFFFFFF);
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// Kernel Segment 0 - Unmapped
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const Addr KSeg0End = ULL(0x9FFFFFFF);
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const Addr KSeg0Base = ULL(0x80000000);
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const Addr KSeg0Mask = ULL(0x1FFFFFFF);
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// Kernel Segment 1 - Unmapped, Uncached
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const Addr KSeg1End = ULL(0xBFFFFFFF);
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const Addr KSeg1Base = ULL(0xA0000000);
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const Addr KSeg1Mask = ULL(0x1FFFFFFF);
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// Kernel/Supervisor Segment - Mapped
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const Addr KSSegEnd = ULL(0xDFFFFFFF);
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const Addr KSSegBase = ULL(0xC0000000);
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// Kernel Segment 3 - Mapped
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const Addr KSeg3End = ULL(0xFFFFFFFF);
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const Addr KSeg3Base = ULL(0xE0000000);
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// For loading... XXX This maybe could be USegEnd?? --ali
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const Addr LoadAddrMask = ULL(0xffffffffff);
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inline Addr Phys2K0Seg(Addr addr)
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{
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return addr | KSeg0Base;
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}
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const unsigned VABits = 32;
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const unsigned PABits = 32; // Is this correct?
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const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
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const Addr VAddrUnImplMask = ~VAddrImplMask;
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inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
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inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
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inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
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const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
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////////////////////////////////////////////////////////////////////////
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//
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// Interrupt levels
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//
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enum InterruptLevels
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{
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INTLEVEL_SOFTWARE_MIN = 4,
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INTLEVEL_SOFTWARE_MAX = 19,
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INTLEVEL_EXTERNAL_MIN = 20,
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INTLEVEL_EXTERNAL_MAX = 34,
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INTLEVEL_IRQ0 = 20,
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INTLEVEL_IRQ1 = 21,
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INTINDEX_ETHERNET = 0,
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INTINDEX_SCSI = 1,
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INTLEVEL_IRQ2 = 22,
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INTLEVEL_IRQ3 = 23,
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INTLEVEL_SERIAL = 33,
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NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
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};
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// MIPS modes
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enum mode_type
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{
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mode_kernel = 0, // kernel
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mode_supervisor = 1, // supervisor
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mode_user = 2, // user mode
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mode_debug = 3, // debug mode
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mode_number // number of modes
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};
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// return a no-op instruction... used for instruction fetch faults
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const ExtMachInst NoopMachInst = 0x00000000;
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const int LogVMPageSize = 13; // 8K bytes
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const int VMPageSize = (1 << LogVMPageSize);
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const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
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const int MachineBytes = 4;
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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const int ANNOTE_NONE = 0;
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const uint32_t ITOUCH_ANNOTE = 0xffffffff;
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// Memory accesses cannot be unaligned
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const bool HasUnalignedMemAcc = false;
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};
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#endif // __ARCH_MIPS_ISA_TRAITS_HH__
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