29e34a739b
User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.
SConstruct:
Set up SWIG builder & scanner.
Set up symlinking of source files into build directory
(by not disabling the default behavior).
configs/test/test.py:
Rewrite to use new script-driven interface.
Include a sample option.
src/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
SimExit() is now exitSimLoop().
src/cpu/base.cc:
SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
Add SWIG build command for main.i.
Use python/m5 in build dir as source for zip archive...
easy now with file duplication enabled.
src/python/m5/__init__.py:
- Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
- Get rid of argument parsing code; just provide default
option descriptors for user script to call optparse with.
- Don't clutter m5 namespace by sucking in all of m5.config
and m5.objects.
- Move instantiate() function here from config.py.
src/python/m5/config.py:
- Move instantiate() function to __init__.py.
- Param.Foo deferred type lookups must use m5.objects
namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
Support for Python-called simulate() function:
- Use IsExitEvent flag to signal events that want
to exit the simulation loop gracefully (instead of
calling exit() to terminate the process).
- Modify interface to hand exit event object back to
caller so it can be inspected for cause.
src/sim/host.hh:
Add MaxTick constant.
src/sim/main.cc:
Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
Use PYTHONPATH environment var to set module path
(instead of clunky code injection method).
Move main control from here into Python:
- Separate initialization code and simulation loop
into separate functions callable from Python.
- Make Python interpreter invocation more pure (more
like directly invoking interpreter).
Add -i and -p flags (only options on binary itself;
other options processed by Python).
Import readline package when using interactive mode.
src/sim/sim_events.cc:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
src/sim/sim_events.hh:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
Get rid of a few unused constructors.
src/sim/sim_exit.hh:
SimExit() is now exitSimLoop().
Get rid of unused functions.
Add comments.
--HG--
extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
66 lines
3.1 KiB
Python
66 lines
3.1 KiB
Python
from m5.config import *
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from BaseMem import BaseMem
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class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
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class BaseCache(BaseMem):
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type = 'BaseCache'
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adaptive_compression = Param.Bool(False,
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"Use an adaptive compression scheme")
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assoc = Param.Int("associativity")
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block_size = Param.Int("block size in bytes")
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compressed_bus = Param.Bool(False,
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"This cache connects to a compressed memory")
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compression_latency = Param.Latency('0ns',
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"Latency in cycles of compression algorithm")
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do_copy = Param.Bool(False, "perform fast copies in the cache")
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hash_delay = Param.Int(1, "time in cycles of hash access")
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in_bus = Param.Bus(NULL, "incoming bus object")
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lifo = Param.Bool(False,
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"whether this NIC partition should use LIFO repl. policy")
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max_miss_count = Param.Counter(0,
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"number of misses to handle before calling exit")
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mem_trace = Param.MemTraceWriter(NULL,
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"memory trace writer to record accesses")
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mshrs = Param.Int("number of MSHRs (max outstanding requests)")
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out_bus = Param.Bus("outgoing bus object")
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prioritizeRequests = Param.Bool(False,
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"always service demand misses first")
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protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
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repl = Param.Repl(NULL, "replacement policy")
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size = Param.MemorySize("capacity in bytes")
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split = Param.Bool(False, "whether or not this cache is split")
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split_size = Param.Int(0,
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"How many ways of the cache belong to CPU/LRU partition")
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store_compressed = Param.Bool(False,
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"Store compressed data in the cache")
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subblock_size = Param.Int(0,
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"Size of subblock in IIC used for compression")
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tgts_per_mshr = Param.Int("max number of accesses per MSHR")
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trace_addr = Param.Addr(0, "address to trace")
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two_queue = Param.Bool(False,
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"whether the lifo should have two queue replacement")
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write_buffers = Param.Int(8, "number of write buffers")
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prefetch_miss = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Miss stream")
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prefetch_access = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Access stream")
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prefetcher_size = Param.Int(100,
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"Number of entries in the harware prefetch queue")
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prefetch_past_page = Param.Bool(False,
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"Allow prefetches to cross virtual page boundaries")
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prefetch_serial_squash = Param.Bool(False,
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"Squash prefetches with a later time on a subsequent miss")
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prefetch_degree = Param.Int(1,
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"Degree of the prefetch depth")
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prefetch_latency = Param.Tick(10,
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"Latency of the prefetcher")
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prefetch_policy = Param.Prefetch('none',
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"Type of prefetcher to use")
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prefetch_cache_check_push = Param.Bool(True,
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"Check if in cash on push or pop of prefetch queue")
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prefetch_use_cpu_id = Param.Bool(True,
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"Use the CPU ID to seperate calculations of prefetches")
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prefetch_data_accesses_only = Param.Bool(False,
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"Only prefetch on data not on instruction accesses")
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