Andreas Hansson 28a7cea2b3 config: Add XOR hashing to the DRAM channel interleaving ... This patch uses the recently added XOR hashing capabilities for the DRAM channel interleaving. This avoids channel biasing due to strided access patterns.		2015-02-03 14:25:55 -05:00
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Benchmarks.py	arm, tests: Update config files to more recent kernels and create 64-bit regressions.	2014-10-29 23:18:27 -05:00
CacheConfig.py	config: Add --memchecker option	2014-12-23 09:31:18 -05:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	scons: Do not build the InOrderCPU	2015-01-20 08:12:45 -05:00
FSConfig.py	config: arm: fix os_flags	2015-01-30 15:49:34 -06:00
MemConfig.py	config: Add XOR hashing to the DRAM channel interleaving	2015-02-03 14:25:55 -05:00
O3_ARM_v7a.py	cpu: Change writeback modeling for outstanding instructions	2014-09-03 07:42:33 -04:00
Options.py	config: Expose the DRAM ranks as a command-line option	2014-12-23 09:31:18 -05:00
Simulation.py	config: Add options to take/resume from SimPoint checkpoints	2014-12-23 09:31:17 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00