554ddc7c07
This patch simplifies the overall CPU by changing the TLB caches such that they do not forward snoops to the table walker port(s). Note that only ARM and X86 are affected. There is no reason for the ports to snoop as they do not actually take any action, and from a performance point of view we are better of not snooping more than we have to. Should it at a later point be required to snoop for a particular TLB design it is easy enough to add it back. |
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.. | ||
Benchmarks.py | ||
CacheConfig.py | ||
Caches.py | ||
cpu2000.py | ||
CpuConfig.py | ||
FSConfig.py | ||
MemConfig.py | ||
O3_ARM_v7a.py | ||
Options.py | ||
Simulation.py | ||
SysPaths.py |