Curtis Dunham 282cf5807d arm: miscreg refactoring ... Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>		2016-12-19 11:03:27 -06:00
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arch	arm: miscreg refactoring	2016-12-19 11:03:27 -06:00
base	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	2016-11-30 17:10:28 -05:00
cpu	cpu: Change traffic generators to use different values for writes	2016-12-05 16:48:20 -05:00
dev	dev: Include DmaDevice in NULL builds	2016-12-19 16:25:38 +00:00
doc	sim: Adding support for power models	2016-06-06 17:16:44 +01:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
gpu-compute	hsail: remove the panic guarding function directives	2016-12-02 18:01:42 -05:00
kern	alpha: Remove ALPHA tru64 support and associated tests	2016-11-17 04:54:14 -05:00
mem	mem: Make the BaseXBar public to not confuse Python wrappers	2016-12-19 16:25:40 +00:00
proto	cpu: Support virtual addr in elastic traces	2015-12-07 16:42:16 -06:00
python	python: Export periodicStatDump	2016-12-19 16:25:39 +00:00
sim	sim: Remove redundant buildEnv import	2016-12-19 16:25:37 +00:00
unittest	style: remove trailing whitespace	2016-02-06 17:21:18 -08:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	scons: fix sanitizer flags with multiple sanitizers	2016-11-28 12:44:54 -05:00