5eab6c4b41
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
62 lines
2.9 KiB
Text
62 lines
2.9 KiB
Text
from BaseMem import BaseMem
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class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
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simobj BaseCache(BaseMem):
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type = 'BaseCache'
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adaptive_compression = Param.Bool(False,
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"Use an adaptive compression scheme")
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assoc = Param.Int("associativity")
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block_size = Param.Int("block size in bytes")
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compressed_bus = Param.Bool(False,
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"This cache connects to a compressed memory")
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compression_latency = Param.Latency('0c',
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"Latency in cycles of compression algorithm")
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do_copy = Param.Bool(False, "perform fast copies in the cache")
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hash_delay = Param.Int(1, "time in cycles of hash access")
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in_bus = Param.Bus(NULL, "incoming bus object")
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lifo = Param.Bool(False,
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"whether this NIC partition should use LIFO repl. policy")
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max_miss_count = Param.Counter(0,
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"number of misses to handle before calling exit")
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mshrs = Param.Int("number of MSHRs (max outstanding requests)")
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out_bus = Param.Bus("outgoing bus object")
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prioritizeRequests = Param.Bool(False,
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"always service demand misses first")
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protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
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repl = Param.Repl(NULL, "replacement policy")
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size = Param.MemorySize("capacity in bytes")
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split = Param.Bool(False, "whether or not this cache is split")
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split_size = Param.Int(0,
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"How many ways of the cache belong to CPU/LRU partition")
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store_compressed = Param.Bool(False,
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"Store compressed data in the cache")
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subblock_size = Param.Int(0,
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"Size of subblock in IIC used for compression")
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tgts_per_mshr = Param.Int("max number of accesses per MSHR")
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trace_addr = Param.Addr(0, "address to trace")
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two_queue = Param.Bool(False,
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"whether the lifo should have two queue replacement")
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write_buffers = Param.Int(8, "number of write buffers")
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prefetch_miss = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Miss stream")
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prefetch_access = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Access stream")
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prefetcher_size = Param.Int(100,
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"Number of entries in the harware prefetch queue")
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prefetch_past_page = Param.Bool(False,
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"Allow prefetches to cross virtual page boundaries")
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prefetch_serial_squash = Param.Bool(False,
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"Squash prefetches with a later time on a subsequent miss")
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prefetch_degree = Param.Int(1,
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"Degree of the prefetch depth")
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prefetch_latency = Param.Tick(10,
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"Latency of the prefetcher")
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prefetch_policy = Param.Prefetch('none',
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"Type of prefetcher to use")
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prefetch_cache_check_push = Param.Bool(True,
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"Check if in cash on push or pop of prefetch queue")
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prefetch_use_cpu_id = Param.Bool(True,
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"Use the CPU ID to seperate calculations of prefetches")
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prefetch_data_accesses_only = Param.Bool(False,
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"Only prefetch on data not on instruction accesses")
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