221 lines
7.6 KiB
C++
221 lines
7.6 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2007 MIPS Technologies, Inc.
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Korey Sewell
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////////////////////////////////////////////////////////////////////
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//
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// MT instructions
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//
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output header {{
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/**
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* Base class for MIPS MT ASE operations.
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*/
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class MTOp : public MipsStaticInst
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{
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protected:
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/// Constructor
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MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass), user_mode(false)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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bool user_mode;
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};
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class MTUserModeOp : public MTOp
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{
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protected:
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/// Constructor
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MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MTOp(mnem, _machInst, __opClass)
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{
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user_mode = true;
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}
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//std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) {
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ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
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} else if (strcmp(mnemonic,"mftgpr") == 0) {
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ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
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} else {
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ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
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}
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return ss.str();
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}
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}};
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output exec {{
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void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0)
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{
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vpe_conf0 = xc->readMiscReg(VPEConf0);
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tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag);
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tc_bind = xc->readMiscReg(TCBind);
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vpe_control = xc->readMiscReg(VPEControl);
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mvp_conf0 = xc->readMiscReg(MVPConf0);
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}
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void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
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{
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config3 = xc->readMiscReg(Config3);
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}
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}};
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def template ThreadRegisterExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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int64_t data;
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%(op_decl)s;
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%(op_rd)s;
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unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0;
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getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0);
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if (isCoprocessorEnabled(xc, 0)) {
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if (bits(vpe_conf0, VPEC0_MVP) == 0 &&
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bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) !=
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bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
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data = -1;
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} else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) >
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bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) {
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data = -1;
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} else {
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int top_bit = 0;
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int bottom_bit = 0;
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if (MT_H == 1) {
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top_bit = 63;
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bottom_bit = 32;
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} else {
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top_bit = 31;
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bottom_bit = 0;
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}
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%(code)s;
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}
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} else {
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fault = new CoprocessorUnusableFault(0);
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MTExecute{{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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unsigned config3;
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getMTExValues(xc, config3);
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if (isCoprocessorEnabled(xc, 0)) {
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if (bits(config3, CFG3_MT) == 1) {
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%(code)s;
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} else {
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fault = new ReservedInstructionFault();
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}
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} else {
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fault = new CoprocessorUnusableFault(0);
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Primary format for integer operate instructions:
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def format MT_Control(code, *opt_flags) {{
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inst_flags = ('IsNonSpeculative', )
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op_type = 'MTOp'
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for x in opt_flags:
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if x == 'UserMode':
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op_type = 'MTUserModeOp'
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else:
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inst_flags += (x, )
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iop = InstObjParams(name, Name, op_type, code, inst_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = MTExecute.subst(iop)
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}};
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def format MT_MFTR(code, *flags) {{
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flags += ('IsNonSpeculative', )
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# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
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code += 'if (MT_H == 1) {\n'
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code += 'data = bits(data, top_bit, bottom_bit);\n'
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code += '}\n'
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code += 'Rd = data;\n'
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iop = InstObjParams(name, Name, 'MTOp', code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = ThreadRegisterExecute.subst(iop)
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}};
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def format MT_MTTR(code, *flags) {{
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flags += ('IsNonSpeculative', )
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# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
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iop = InstObjParams(name, Name, 'MTOp', code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = ThreadRegisterExecute.subst(iop)
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}};
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