Gabe Black 3e8e813218 CPU: Separate out native trace into ISA (in)dependent code and SimObjects. ... --HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py		2009-07-19 23:54:56 -07:00
..
alpha	Alpha: Missed a file in an earlier changeset.	2009-07-09 00:20:41 -07:00
arm	ARM: Fix the "open" flag constants.	2009-07-14 21:03:33 -07:00
mips	ISAs: Get rid of the IControl operand type.	2009-07-10 01:21:04 -07:00
sparc	CPU: Separate out native trace into ISA (in)dependent code and SimObjects.	2009-07-19 23:54:56 -07:00
x86	CPU: Separate out native trace into ISA (in)dependent code and SimObjects.	2009-07-19 23:54:56 -07:00
isa_parser.py	ISAs: Get rid of the IControl operand type.	2009-07-10 01:21:04 -07:00
isa_specific.hh	style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs	2008-09-10 14:26:15 -04:00
micro_asm.py	Microcode: Fix a silent typo error in the microcode assembler.	2008-10-09 00:07:38 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	Registers: Add a registers.hh file as an ISA switched header.	2009-07-08 23:02:21 -07:00