187 lines
3.4 KiB
INI
187 lines
3.4 KiB
INI
[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu dvfs_handler membus monitor physmem
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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exit_on_work_items=false
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init_param=0
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kernel=
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kernel_addr_check=true
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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mem_ranges=
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memories=system.physmem
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mmap_using_noreserve=false
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multi_thread=false
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num_work_ids=16
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readfile=
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symbolfile=
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thermal_components=
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thermal_model=Null
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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[system.clk_domain]
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type=SrcClockDomain
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children=voltage_domain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.clk_domain.voltage_domain
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[system.clk_domain.voltage_domain]
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type=VoltageDomain
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eventq_index=0
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voltage=1.000000
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[system.cpu]
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type=TrafficGen
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clk_domain=system.clk_domain
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config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
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elastic_req=false
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eventq_index=0
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system=system
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port=system.monitor.slave
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[system.dvfs_handler]
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type=DVFSHandler
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domains=
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enable=false
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eventq_index=0
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sys_clk_domain=system.clk_domain
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transition_latency=100000000
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[system.membus]
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type=NoncoherentXBar
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clk_domain=system.clk_domain
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eventq_index=0
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forward_latency=1
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frontend_latency=2
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response_latency=2
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use_default_range=false
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width=16
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master=system.physmem.port
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slave=system.monitor.master system.system_port
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[system.monitor]
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type=CommMonitor
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bandwidth_bins=20
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burst_length_bins=20
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clk_domain=system.clk_domain
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disable_addr_dists=true
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disable_bandwidth_hists=false
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disable_burst_length_hists=false
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disable_itt_dists=false
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disable_latency_hists=false
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disable_outstanding_hists=false
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disable_transaction_hists=false
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eventq_index=0
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itt_bins=20
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itt_max_bin=100000
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latency_bins=20
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outstanding_bins=20
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read_addr_mask=18446744073709551615
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sample_period=1000000000
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system=system
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transaction_bins=20
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write_addr_mask=18446744073709551615
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master=system.membus.slave[0]
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slave=system.cpu.port
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[system.physmem]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
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addr_mapping=RoRaBaCoCh
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bank_groups_per_rank=0
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banks_per_rank=8
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burst_length=8
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channels=1
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clk_domain=system.clk_domain
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conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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device_size=536870912
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devices_per_rank=8
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dll=true
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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mem_sched_policy=frfcfs
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min_writes_per_switch=16
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null=false
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page_policy=open_adaptive
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCCD_L=0
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tCK=1250
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tCL=13750
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tCS=2500
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=260000
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tRP=13750
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tRRD=6000
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tRRD_L=0
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=30000
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tXP=0
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tXPDLL=0
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tXS=0
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tXSDLL=0
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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port=system.membus.master[0]
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