1785 lines
205 KiB
Text
1785 lines
205 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.982585 # Number of seconds simulated
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sim_ticks 1982585357000 # Number of ticks simulated
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final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1043358 # Simulator instruction rate (inst/s)
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host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 33918612914 # Simulator tick rate (ticks/s)
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host_mem_usage 377952 # Number of bytes of host memory used
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host_seconds 58.45 # Real time elapsed on the host
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sim_insts 60985541 # Number of instructions simulated
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sim_ops 60985541 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 407445 # Number of read requests accepted
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system.physmem.writeReqs 120910 # Number of write requests accepted
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system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25232 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25377 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25433 # Per bank write bursts
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system.physmem.perBankRdBursts::3 24853 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25156 # Per bank write bursts
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system.physmem.perBankRdBursts::5 25421 # Per bank write bursts
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system.physmem.perBankRdBursts::6 25501 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25341 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25248 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25578 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25745 # Per bank write bursts
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system.physmem.perBankRdBursts::11 25922 # Per bank write bursts
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system.physmem.perBankRdBursts::12 25991 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25558 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25312 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25655 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7850 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7774 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7467 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6887 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7102 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7345 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7434 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7145 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7156 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7306 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7741 # Per bank write bursts
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system.physmem.perBankWrBursts::11 8153 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8257 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7909 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7539 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7820 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 21 # Number of times write queue was full causing retry
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system.physmem.totGap 1982577992500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 407445 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 120910 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 2792890500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.13 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 363877 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 96767 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3752359.67 # Average gap between requests
|
|
system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 671.011108 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 671.118945 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 7416955 # DTB read hits
|
|
system.cpu0.dtb.read_misses 7442 # DTB read misses
|
|
system.cpu0.dtb.read_acv 210 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 490672 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 5004564 # DTB write hits
|
|
system.cpu0.dtb.write_misses 812 # DTB write misses
|
|
system.cpu0.dtb.write_acv 134 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 187451 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 12421519 # DTB hits
|
|
system.cpu0.dtb.data_misses 8254 # DTB misses
|
|
system.cpu0.dtb.data_acv 344 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 678123 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 3482641 # ITB hits
|
|
system.cpu0.itb.fetch_misses 3871 # ITB misses
|
|
system.cpu0.itb.fetch_acv 184 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 3486512 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numCycles 3964851833 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 47325532 # Number of instructions committed
|
|
system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1185742 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 43895499 # number of integer instructions
|
|
system.cpu0.num_fp_insts 207106 # number of float instructions
|
|
system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 12461430 # number of memory refs
|
|
system.cpu0.num_load_insts 7443904 # Number of load instructions
|
|
system.cpu0.num_store_insts 5017526 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles
|
|
system.cpu0.Branches 7135463 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 47334130 # Class of executed instruction
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
|
|
system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 222 # number of syscalls executed
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 147613 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1281
|
|
system.cpu0.kern.mode_good::user 1281
|
|
system.cpu0.kern.mode_good::idle 0
|
|
system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 3027 # number of times the context was actually changed
|
|
system.cpu0.dcache.tags.replacements 1172695 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 672708 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 1183219 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183219 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 1183219 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41944853000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41944853000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 686863 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 46646633 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 687497 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 2508569 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2993 # DTB read misses
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 239364 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 1828737 # DTB write hits
|
|
system.cpu1.dtb.write_misses 342 # DTB write misses
|
|
system.cpu1.dtb.write_acv 29 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 105248 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 4337306 # DTB hits
|
|
system.cpu1.dtb.data_misses 3335 # DTB misses
|
|
system.cpu1.dtb.data_acv 29 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 344612 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 1989876 # ITB hits
|
|
system.cpu1.itb.fetch_misses 1216 # ITB misses
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 1991092 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numCycles 3965170714 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 13660009 # Number of instructions committed
|
|
system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 429702 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 12598388 # number of integer instructions
|
|
system.cpu1.num_fp_insts 178445 # number of float instructions
|
|
system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 4361445 # number of memory refs
|
|
system.cpu1.num_load_insts 2523214 # Number of load instructions
|
|
system.cpu1.num_store_insts 1838231 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles
|
|
system.cpu1.Branches 1945174 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 13663373 # Class of executed instruction
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed
|
|
system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
|
|
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
|
|
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
|
|
system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
|
|
system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
|
|
system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
|
|
system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
|
|
system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
|
|
system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
|
|
system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
|
|
system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
|
|
system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
|
|
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::total 104 # number of syscalls executed
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 73942 # number of callpals executed
|
|
system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches
|
|
system.cpu1.kern.mode_good::kernel 911
|
|
system.cpu1.kern.mode_good::user 464
|
|
system.cpu1.kern.mode_good::idle 447
|
|
system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 2065 # number of times the context was actually changed
|
|
system.cpu1.dcache.tags.replacements 173710 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 189082 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 119711 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 331160 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 13331662 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 331712 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7379 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7379 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 55683 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 55683 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41695 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375543 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375543 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 175 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
|
|
system.iocache.overall_misses::total 175 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
|
system.iocache.writebacks::total 41520 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 341926 # number of replacements
|
|
system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 35906123 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 35906123 # Number of data accesses
|
|
system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 792419 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 124095 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 48625 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 172720 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 674900 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 330771 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1005671 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 659420 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 113743 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 674900 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 783515 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 330771 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 162368 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1951554 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 674900 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 783515 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 330771 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 162368 # number of overall hits
|
|
system.l2c.overall_hits::total 1951554 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 2967 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1808 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 925 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 929 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1854 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 7864 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 122834 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 12571 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 940 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 13511 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 271540 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 337 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 271877 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 12571 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 386510 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 940 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 8201 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 408222 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 12571 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 386510 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 940 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 8201 # number of overall misses
|
|
system.l2c.overall_misses::total 408222 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 3901500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 36480500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 40382000 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3643000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1056500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 4699500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 14617384500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1036956000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 15654340500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1651627500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 124696500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 1776324000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 33670754500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 43654000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 33714408500 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 1651627500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 48288139000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 124696500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1080610000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 51145073000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 1651627500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 48288139000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 124696500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1080610000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 51145073000 # number of overall miss cycles
|
|
system.l2c.Writeback_accesses::writebacks 792419 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 792419 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 2365 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 5518 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 964 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 953 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1917 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 239065 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 56489 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 295554 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 687471 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 331711 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1019182 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 930960 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 114080 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 1045040 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 687471 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1170025 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 331711 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 170569 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2359776 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 687471 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1170025 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 331711 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 170569 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2359776 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941009 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764482 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.865350 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.959544 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974816 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.967136 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.480915 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.139213 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.415606 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018286 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002834 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.013257 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291677 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002954 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.260159 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.018286 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.330343 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.002834 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.048080 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.172992 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.018286 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.330343 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.002834 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.048080 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.172992 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1314.964611 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20177.267699 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 8456.963351 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3938.378378 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1137.244349 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 2534.789644 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127140.858485 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131861.139369 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 127443.057297 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131383.939225 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132655.851064 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 131472.429872 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123999.243205 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 129537.091988 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 124006.107541 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 131383.939225 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 124933.737808 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 132655.851064 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 131765.638337 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 125287.399993 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 131383.939225 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 124933.737808 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 132655.851064 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 131765.638337 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 125287.399993 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 79390 # number of writebacks
|
|
system.l2c.writebacks::total 79390 # number of writebacks
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 324 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 324 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2967 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1808 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 4775 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 925 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 929 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1854 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 114970 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 7864 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 122834 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12571 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 929 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 13500 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271540 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 337 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 271877 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 12571 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 386510 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 929 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 8201 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 408211 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 12571 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 386510 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 929 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 8201 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 408211 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 7204 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 14131 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 21335 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 212307500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 129803000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 342110500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 65706500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 66436000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 132142500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13467684500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958316000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 14426000500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1525917500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 114051500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 1639969000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30955354500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 40284000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 30995638500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 1525917500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 44423039000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 114051500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 998600000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 47061608000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 1525917500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 44423039000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 114051500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 998600000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 47061608000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1400094000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22239000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 1422333000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2192043000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 708908500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 2900951500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3592137000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 731147500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4323284500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 7204 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 292756 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 14131 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 14131 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 120910 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 262059 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 123180 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 122316 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 22736 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 883364 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 883364 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 484490 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
---------- End Simulation Statistics ----------
|