1006 lines
115 KiB
Text
1006 lines
115 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.079190 # Number of seconds simulated
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sim_ticks 79190347500 # Number of ticks simulated
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final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 91850 # Simulator instruction rate (inst/s)
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host_op_rate 153949 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 55073733 # Simulator tick rate (ticks/s)
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host_mem_usage 350132 # Number of bytes of host memory used
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host_seconds 1437.90 # Real time elapsed on the host
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sim_insts 132071192 # Number of instructions simulated
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sim_ops 221363384 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory
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system.physmem.bytes_read::total 345920 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 5405 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 299 # Per bank write bursts
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system.physmem.perBankRdBursts::1 345 # Per bank write bursts
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system.physmem.perBankRdBursts::2 461 # Per bank write bursts
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system.physmem.perBankRdBursts::3 350 # Per bank write bursts
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system.physmem.perBankRdBursts::4 340 # Per bank write bursts
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system.physmem.perBankRdBursts::5 325 # Per bank write bursts
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system.physmem.perBankRdBursts::6 403 # Per bank write bursts
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system.physmem.perBankRdBursts::7 384 # Per bank write bursts
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system.physmem.perBankRdBursts::8 342 # Per bank write bursts
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system.physmem.perBankRdBursts::9 281 # Per bank write bursts
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system.physmem.perBankRdBursts::10 239 # Per bank write bursts
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system.physmem.perBankRdBursts::11 284 # Per bank write bursts
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system.physmem.perBankRdBursts::12 217 # Per bank write bursts
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system.physmem.perBankRdBursts::13 467 # Per bank write bursts
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system.physmem.perBankRdBursts::14 385 # Per bank write bursts
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system.physmem.perBankRdBursts::15 283 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 79190259000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 5405 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation
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system.physmem.totQLat 39419500 # Total ticks spent queuing
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system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.03 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 4299 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 14651296.76 # Average gap between requests
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system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ)
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system.physmem_0.averagePower 669.530615 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ)
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system.physmem_1.averagePower 669.149179 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states
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system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu.branchPred.lookups 20589195 # Number of BP lookups
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system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
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system.cpu.workload.num_syscalls 400 # Number of system calls
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system.cpu.numCycles 158380696 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing
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system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb
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system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued
|
|
system.cpu.iq.rate 1.637565 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 14327856 # Number of branches executed
|
|
system.cpu.iew.exec_stores 22278532 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.624539 # Inst execution rate
|
|
system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 204348842 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
|
|
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 77165304 # Number of memory references committed
|
|
system.cpu.commit.loads 56649587 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 12326938 # Number of branches committed
|
|
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 797818 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 455802776 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 648723400 # The number of ROB writes
|
|
system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
|
|
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 448507967 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 232568909 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 52 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 65736393 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2848 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 10 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 549 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 551 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 551 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 551 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 4970 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1639.175035 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 24244955 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 6947 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3489.989204 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1639.175035 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.800378 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.800378 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 24244955 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 24244955 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 9408 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 9408 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 9408 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 9408 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 9408 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 9408 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 407324999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 407324999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 407324999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 407324999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 407324999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 407324999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 24254363 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 24254363 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 24254363 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 24254363 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 24254363 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 24254363 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43295.599384 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 43295.599384 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 43295.599384 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 43295.599384 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 788 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 65.666667 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2164 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2164 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2164 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2164 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2164 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2164 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7244 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 7244 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 7244 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 7244 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 7244 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 7244 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 309481499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 309481499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 309481499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 309481499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 309481499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 309481499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42722.459829 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42722.459829 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 2588.929088 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 8413 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 3873 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.172218 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 1.256976 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.894376 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 304.777736 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000038 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069668 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009301 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3873 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 39 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2616 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118195 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 118429 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 118429 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3494 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 3494 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 40 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3494 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3540 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3494 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3540 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 296 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 296 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1534 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1534 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3451 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 3451 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 421 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 421 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3451 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1955 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 5406 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3451 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1955 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 5406 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114989000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 114989000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261344500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 261344500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34980500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 34980500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 261344500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 149969500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 411314000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 261344500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 149969500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 411314000 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 296 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 296 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1540 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1540 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6945 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 6945 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 461 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 461 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 6945 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2001 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8946 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 6945 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2001 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8946 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996104 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.996104 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.496904 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.496904 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.913232 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.913232 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.496904 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.977011 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.604292 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.496904 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.977011 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.604292 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74960.234681 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74960.234681 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75730.078238 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75730.078238 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83089.073634 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83089.073634 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 76084.720681 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 76084.720681 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 296 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 296 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1534 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1534 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3451 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3451 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 421 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 421 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3451 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1955 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 5406 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3451 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1955 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 5406 # number of overall MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6416500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6416500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99649000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99649000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226844500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226844500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30770500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30770500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226844500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130419500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 357264000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226844500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130419500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 357264000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996104 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996104 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.496904 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.913232 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.913232 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.604292 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.604292 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21677.364865 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21677.364865 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64960.234681 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64960.234681 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65732.975949 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65732.975949 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73089.073634 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 299 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 3871 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 296 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 296 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 1534 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 1534 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 5701 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 5701 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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