1532 lines
177 KiB
Text
1532 lines
177 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.875745 # Number of seconds simulated
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sim_ticks 1875745192000 # Number of ticks simulated
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final_tick 1875745192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 131976 # Simulator instruction rate (inst/s)
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host_op_rate 131976 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4672432142 # Simulator tick rate (ticks/s)
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host_mem_usage 378172 # Number of bytes of host memory used
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host_seconds 401.45 # Real time elapsed on the host
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sim_insts 52981683 # Number of instructions simulated
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sim_ops 52981683 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 962112 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24881536 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25844608 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 962112 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 962112 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7523648 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7523648 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15033 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388774 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 403822 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 117557 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117557 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 512923 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13264881 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13778315 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 512923 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 512923 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4011018 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4011018 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4011018 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 512923 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13264881 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17789333 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 403822 # Number of read requests accepted
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system.physmem.writeReqs 117557 # Number of write requests accepted
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system.physmem.readBursts 403822 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 117557 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25836864 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7522176 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25844608 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7523648 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25633 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25421 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25565 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25492 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25387 # Per bank write bursts
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system.physmem.perBankRdBursts::5 24737 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24937 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25080 # Per bank write bursts
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system.physmem.perBankRdBursts::8 24933 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25019 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25561 # Per bank write bursts
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system.physmem.perBankRdBursts::11 24878 # Per bank write bursts
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system.physmem.perBankRdBursts::12 24487 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25242 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25745 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25584 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7946 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7515 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7960 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7517 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7330 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6676 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6762 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6719 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7146 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6702 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7407 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6970 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7148 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7861 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8061 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7814 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 19 # Number of times write queue was full causing retry
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system.physmem.totGap 1875739913500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 403822 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 117557 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 315399 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 36013 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 28212 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 23984 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 76 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1634 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1915 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3287 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4150 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5413 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 6026 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::22 6352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 8246 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 9376 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 8640 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::27 8795 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7819 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 6510 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::31 6491 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::32 5735 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 222 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 259 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 149 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 139 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 115 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 93 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 110 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 62141 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 536.822002 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 331.292900 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 411.615573 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 13686 22.02% 22.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 10474 16.86% 38.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4974 8.00% 46.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2759 4.44% 51.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2428 3.91% 55.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1656 2.66% 57.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 3743 6.02% 63.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1149 1.85% 65.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 21272 34.23% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 62141 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5219 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 77.350259 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 2906.647984 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-8191 5216 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5219 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5219 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 22.520406 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 19.103659 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 21.296995 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 4441 85.09% 85.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 172 3.30% 88.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 18 0.34% 88.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 180 3.45% 92.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 4 0.08% 92.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 21 0.40% 92.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 36 0.69% 93.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 2 0.04% 93.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 12 0.23% 93.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 25 0.48% 94.10% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 3 0.06% 94.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 4 0.08% 94.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 11 0.21% 94.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 4 0.08% 94.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 20 0.38% 94.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 29 0.56% 95.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 1 0.02% 95.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 29 0.56% 96.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 164 3.14% 99.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 1 0.02% 99.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 5 0.10% 99.33% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 3 0.06% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 6 0.11% 99.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 4 0.08% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 1 0.02% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-171 4 0.08% 99.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 11 0.21% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::196-199 1 0.02% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5219 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 4201414500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 11770808250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2018505000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 10407.24 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 29157.24 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 363834 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 95259 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 81.03 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3597651.45 # Average gap between requests
|
|
system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 233286480 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 127289250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1577565600 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 378594000 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 61659983700 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1071355704750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1257846562020 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 670.587193 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1782093997750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 62635040000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 31009992250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 236499480 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 129042375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1571255400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 383026320 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 61488464715 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1071506168250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1257828594780 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 670.577609 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1782344410500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 62635040000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 30760024500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 17977610 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 15676073 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 370677 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 11479744 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5859077 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 51.038394 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 912903 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 21206 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 10250294 # DTB read hits
|
|
system.cpu.dtb.read_misses 41452 # DTB read misses
|
|
system.cpu.dtb.read_acv 531 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 965916 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6642949 # DTB write hits
|
|
system.cpu.dtb.write_misses 9723 # DTB write misses
|
|
system.cpu.dtb.write_acv 398 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 342082 # DTB write accesses
|
|
system.cpu.dtb.data_hits 16893243 # DTB hits
|
|
system.cpu.dtb.data_misses 51175 # DTB misses
|
|
system.cpu.dtb.data_acv 929 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1307998 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1771116 # ITB hits
|
|
system.cpu.itb.fetch_misses 27251 # ITB misses
|
|
system.cpu.itb.fetch_acv 655 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1798367 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 153807945 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 29589963 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 78082078 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 17977610 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 6771980 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 115315004 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1233982 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 2306 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 29550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1247451 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 470617 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 460 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 8997640 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 271780 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 147272342 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.530188 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.786973 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 132738967 90.13% 90.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 930397 0.63% 90.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1956016 1.33% 92.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 907001 0.62% 92.71% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2772714 1.88% 94.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 615474 0.42% 95.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 727209 0.49% 95.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1009346 0.69% 96.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 5615218 3.81% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 147272342 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.116883 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.507660 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 24002291 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 111345789 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 9440793 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 1908530 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 574938 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 581140 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 42414 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 68062016 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 132549 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 574938 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 24926396 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 78168566 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 21593766 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 10339140 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 11669534 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 65637228 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 204564 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2092706 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 229144 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 7400964 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 43743792 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 79597549 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 79416724 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 168373 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38181235 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 5562549 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1689699 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 239435 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13568621 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 10378795 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 6951631 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1513940 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1098335 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 58473138 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2139162 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 57493462 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 7630612 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 3411321 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1477941 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 147272342 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.390389 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.114131 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 123663895 83.97% 83.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 10186331 6.92% 90.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 4292878 2.91% 93.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 3019293 2.05% 95.85% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 3081041 2.09% 97.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1488323 1.01% 98.95% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1011420 0.69% 99.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 404091 0.27% 99.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 125070 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 147272342 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 210189 18.68% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 539111 47.92% 66.61% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 375615 33.39% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 39049173 67.92% 67.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 61879 0.11% 68.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 10660314 18.54% 86.65% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6723536 11.69% 98.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 949085 1.65% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 57493462 # Type of FU issued
|
|
system.cpu.iq.rate 0.373800 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1124915 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.019566 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 262728196 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 67925320 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55850502 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 713041 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 336604 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 329051 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 58228243 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 382848 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 635438 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1285740 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3115 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 19427 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 573353 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18203 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 457581 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 574938 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 74485816 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1122121 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 64302959 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 140159 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 10378795 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 6951631 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1891041 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 44126 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 874685 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 19427 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 179710 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 409314 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 589024 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 56907888 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 10319427 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 585573 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3690659 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 16987198 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 8973802 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6667771 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.369993 # Inst execution rate
|
|
system.cpu.iew.wb_sent 56315493 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 56179553 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 28757989 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 39945326 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.365258 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.719934 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 8014233 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 661221 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 539644 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 145865842 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.385097 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.287358 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 126089885 86.44% 86.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 7851403 5.38% 91.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4272179 2.93% 94.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2235192 1.53% 96.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1747101 1.20% 97.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 615790 0.42% 97.91% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 475839 0.33% 98.23% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 478833 0.33% 98.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2099620 1.44% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 145865842 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 56172516 # Number of instructions committed
|
|
system.cpu.commit.committedOps 56172516 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15471333 # Number of memory references committed
|
|
system.cpu.commit.loads 9093055 # Number of loads committed
|
|
system.cpu.commit.membars 226352 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8440752 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52021823 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 740586 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 3198106 5.69% 5.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 36219281 64.48% 70.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 60683 0.11% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 9319407 16.59% 86.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 6384233 11.37% 98.31% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 949085 1.69% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 56172516 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 2099620 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 207703277 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 129775597 # The number of ROB writes
|
|
system.cpu.timesIdled 576321 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 6535603 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 3597682440 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 52981683 # Number of Instructions Simulated
|
|
system.cpu.committedOps 52981683 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 2.903040 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.903040 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.344466 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.344466 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 74566924 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 40527176 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 167101 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 167535 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1985778 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 939467 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 1402095 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.992786 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 11832212 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1402607 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 8.435871 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.992786 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 63847952 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 63847952 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7239475 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7239475 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4190405 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4190405 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 186164 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 186164 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215734 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 215734 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 11429880 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 11429880 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 11429880 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 11429880 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1798792 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1798792 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1957410 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1957410 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23330 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 23330 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3756202 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3756202 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3756202 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3756202 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57198715500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 57198715500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 116967363039 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 116967363039 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 446591500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 446591500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 850000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 850000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 174166078539 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 174166078539 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 174166078539 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 174166078539 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9038267 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9038267 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6147815 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6147815 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209494 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 209494 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215760 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215760 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15186082 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15186082 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15186082 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15186082 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199020 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.199020 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318391 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.318391 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111364 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111364 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.247345 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.247345 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.247345 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.247345 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31798.404429 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 31798.404429 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59756.189577 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 59756.189577 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19142.370339 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19142.370339 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 46367.601779 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 46367.601779 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 7156530 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 5457 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 133923 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437647 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 188.172414 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 841276 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 841276 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 704782 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 704782 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666649 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1666649 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5284 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5284 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2371431 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2371431 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2371431 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2371431 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1094010 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1094010 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290761 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 290761 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18046 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 18046 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1384771 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1384771 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1384771 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1384771 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44554526500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 44554526500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18468782348 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 18468782348 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 228783500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 228783500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 824000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 824000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63023308848 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 63023308848 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63023308848 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 63023308848 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450570000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450570000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2036143500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2036143500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486713500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486713500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121042 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121042 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047295 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047295 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086141 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086141 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091187 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091187 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40725.885961 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40725.885961 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63518.774347 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63518.774347 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12677.795633 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12677.795633 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 31692.307692 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 31692.307692 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209317.460317 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209317.460317 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.477599 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.477599 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210957.980397 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210957.980397 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1038950 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 507.834309 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 7904301 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1039458 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 7.604252 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 42289841500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 507.834309 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.991864 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.991864 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 10037466 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 10037466 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 7904302 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7904302 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 7904302 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7904302 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 7904302 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7904302 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1093336 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1093336 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1093336 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1093336 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1093336 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1093336 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16294267486 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 16294267486 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 16294267486 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 16294267486 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 16294267486 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 16294267486 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 8997638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 8997638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 8997638 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 8997638 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 8997638 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 8997638 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.121514 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.121514 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.121514 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.121514 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.257083 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14903.257083 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14903.257083 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14903.257083 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 10533 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 34.993355 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53508 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 53508 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 53508 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 53508 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 53508 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 53508 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039828 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1039828 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1039828 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1039828 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1039828 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1039828 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14359854493 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 14359854493 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14359854493 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 14359854493 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14359854493 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 14359854493 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115567 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.115567 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.115567 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13809.836332 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13809.836332 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 338309 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65280.236813 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4173910 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 403476 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 10.344878 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 9183094000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 53277.296150 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.937838 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6694.002825 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.812947 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081008 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.102142 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.996097 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3483 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3330 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55446 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 39757210 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 39757210 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 841276 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 841276 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 30 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 30 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 19 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 186016 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 186016 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1024478 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1024478 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827309 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 827309 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1024478 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1013325 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2037803 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1024478 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1013325 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2037803 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 98 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 98 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115511 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 115511 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15035 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 15035 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273855 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 273855 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15035 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 389366 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 404401 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15035 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 389366 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 404401 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 804000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 804000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 243500 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 243500 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16132911000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 16132911000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2019085000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2019085000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34002540500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 34002540500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 2019085000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 50135451500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 52154536500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 2019085000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 50135451500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 52154536500 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 841276 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 841276 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 128 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 128 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 301527 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 301527 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1039513 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1039513 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1101164 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 1101164 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1039513 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1402691 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2442204 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1039513 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1402691 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2442204 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.765625 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.765625 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.269231 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.269231 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383087 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383087 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014464 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014464 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248696 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248696 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014464 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277585 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.165589 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014464 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277585 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.165589 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8204.081633 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8204.081633 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139665.581633 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139665.581633 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134292.317925 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134292.317925 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124162.569608 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124162.569608 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134292.317925 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128761.760143 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 128967.377677 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134292.317925 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128761.760143 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 128967.377677 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 76045 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 76045 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 304 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 304 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 98 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 98 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115511 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115511 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15034 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15034 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273855 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273855 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15034 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389366 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 404400 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15034 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389366 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 404400 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7022000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7022000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 499500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 499500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14977801000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14977801000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1868614000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1868614000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31274184500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31274184500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1868614000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46251985500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 48120599500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1868614000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46251985500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 48120599500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363945000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363945000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925742500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925742500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289687500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289687500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.765625 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.765625 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.269231 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.269231 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383087 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383087 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014463 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248696 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248696 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.165588 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71653.061224 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71653.061224 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71357.142857 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71357.142857 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129665.581633 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129665.581633 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124292.536916 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124292.536916 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114199.793686 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114199.793686 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196817.460317 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196817.460317 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.977079 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.977079 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199037.239835 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199037.239835 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 4883718 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2441508 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2147995 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 958852 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 1860290 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 128 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 154 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 301527 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 301527 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039828 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101337 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3117755 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4239617 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7357372 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66528832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143662708 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 210191540 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 422209 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 5321984 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.032932 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 5316206 99.89% 99.89% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 5778 0.11% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 5321984 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3296198000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1561216545 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2115809899 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51150 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 215079498 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.249403 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1725991887000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.249403 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.078088 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.078088 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
|
system.iocache.overall_misses::total 173 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21903883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21903883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427983615 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 5427983615 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 21903883 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 21903883 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 21903883 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 21903883 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 126612.040462 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 126612.040462 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 126612.040462 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13253883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13253883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350383615 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 3350383615 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 13253883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 13253883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 13253883 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 13253883 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 295909 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 117557 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 261789 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 334 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 341 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 115275 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 115275 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 289062 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 83 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146388 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179610 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1304427 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754676 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33412404 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 435 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 842283 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 842283 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 842283 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 28662500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1313672631 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 106500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2139416664 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 69895667 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74668 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182251 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73301 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73301 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148613 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1818203066500 96.93% 96.93% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 62700500 0.00% 96.94% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 538036000 0.03% 96.96% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 56940563000 3.04% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1875744366000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.815430 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175134 91.23% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 191979 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1909
|
|
system.cpu.kern.mode_good::user 1739
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.326325 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29901576500 1.59% 1.59% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2896080000 0.15% 1.75% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1842946701500 98.25% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|