2332 lines
268 KiB
Text
2332 lines
268 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.921764 # Number of seconds simulated
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sim_ticks 1921763645000 # Number of ticks simulated
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final_tick 1921763645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 133766 # Simulator instruction rate (inst/s)
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host_op_rate 133766 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4532754153 # Simulator tick rate (ticks/s)
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host_mem_usage 384052 # Number of bytes of host memory used
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host_seconds 423.97 # Real time elapsed on the host
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sim_insts 56713315 # Number of instructions simulated
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sim_ops 56713315 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 874240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 24774144 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 514944 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26267328 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 874240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 977280 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7875136 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7875136 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 13660 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 387096 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 8046 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 410427 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 123049 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 123049 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 454915 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 12891358 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 53617 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 267954 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13668345 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 454915 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 53617 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 508533 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4097869 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4097869 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4097869 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 454915 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 12891358 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 53617 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 267954 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17766214 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 410427 # Number of read requests accepted
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system.physmem.writeReqs 123049 # Number of write requests accepted
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system.physmem.readBursts 410427 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 123049 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26259904 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7874176 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 26267328 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7875136 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 46661 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25500 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25969 # Per bank write bursts
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system.physmem.perBankRdBursts::2 26011 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25727 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25508 # Per bank write bursts
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system.physmem.perBankRdBursts::5 25811 # Per bank write bursts
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system.physmem.perBankRdBursts::6 25519 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25160 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25451 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25839 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25659 # Per bank write bursts
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system.physmem.perBankRdBursts::11 25030 # Per bank write bursts
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system.physmem.perBankRdBursts::12 26076 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25978 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25473 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25600 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8066 # Per bank write bursts
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system.physmem.perBankWrBursts::1 8046 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8027 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7668 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7376 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7761 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7583 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6991 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7326 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7600 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7532 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7413 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7962 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8267 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7722 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7694 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 18 # Number of times write queue was full causing retry
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system.physmem.totGap 1921759329500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 410427 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 123049 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 317921 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 38025 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 29433 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 24818 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 92 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::16 2006 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::17 3511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 4488 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 5809 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 6814 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 6385 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::22 6758 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::23 8174 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 8527 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 9653 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 8822 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 9133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 8229 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 8839 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::30 6881 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::31 6896 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::32 6046 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 371 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 229 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 237 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 181 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 213 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 136 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 96 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 77 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::63 72 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65305 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 522.687084 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 319.252168 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 410.914363 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 14928 22.86% 22.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 11344 17.37% 40.23% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-383 5465 8.37% 48.60% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 2873 4.40% 53.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2572 3.94% 56.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1636 2.51% 59.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 3782 5.79% 65.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1204 1.84% 67.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 21501 32.92% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 65305 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 5548 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 73.956561 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 2834.723442 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-8191 5545 99.95% 99.95% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5548 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5548 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 22.176280 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 18.947134 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 20.868875 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 4772 86.01% 86.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 155 2.79% 88.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 19 0.34% 89.15% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 186 3.35% 92.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 8 0.14% 92.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 21 0.38% 93.02% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 41 0.74% 93.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 5 0.09% 93.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 18 0.32% 94.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 27 0.49% 94.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 1 0.02% 94.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 5 0.09% 94.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 9 0.16% 94.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 4 0.07% 95.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 20 0.36% 95.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 24 0.43% 95.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 2 0.04% 95.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 29 0.52% 96.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 1 0.02% 96.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 158 2.85% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.04% 99.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 3 0.05% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 2 0.04% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 2 0.04% 99.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 4 0.07% 99.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-171 3 0.05% 99.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 3 0.05% 99.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 14 0.25% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-195 1 0.02% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5548 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 4465229000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 12158560250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2051555000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 10882.55 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 29632.55 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.67 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 369445 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 98595 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.04 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3602335.12 # Average gap between requests
|
|
system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 245919240 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 134182125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1600599000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 398636640 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 63180018945 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1097637063000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1288716655350 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 670.590642 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1825809460500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 64171900000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 31782207000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 247786560 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 135201000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1599826800 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 398623680 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 62993858085 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1097800353750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1288695886275 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 670.579840 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1826084104500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 64171900000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 31507549250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu0.branchPred.lookups 16172722 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 14147320 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 315974 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 10263532 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 5327857 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 51.910561 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 805529 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 17788 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 9178933 # DTB read hits
|
|
system.cpu0.dtb.read_misses 32423 # DTB read misses
|
|
system.cpu0.dtb.read_acv 530 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 683199 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 5878949 # DTB write hits
|
|
system.cpu0.dtb.write_misses 7260 # DTB write misses
|
|
system.cpu0.dtb.write_acv 384 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 235377 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 15057882 # DTB hits
|
|
system.cpu0.dtb.data_misses 39683 # DTB misses
|
|
system.cpu0.dtb.data_acv 914 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 918576 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 1433805 # ITB hits
|
|
system.cpu0.itb.fetch_misses 20098 # ITB misses
|
|
system.cpu0.itb.fetch_acv 602 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 1453903 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numCycles 146988157 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 26434329 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 70323281 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 16172722 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 6133386 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 112438747 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 1062414 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 847 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 30229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 925731 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 462393 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 403 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 8125656 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 231201 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 140823886 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.499370 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 1.736005 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 127673480 90.66% 90.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 835079 0.59% 91.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 1817427 1.29% 92.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 778983 0.55% 93.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 2600412 1.85% 94.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 568090 0.40% 95.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 652333 0.46% 95.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 824353 0.59% 96.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 5073729 3.60% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 140823886 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.110027 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.478428 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 21407057 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 108692435 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 8462793 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 1765937 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 495663 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 515138 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 35957 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 61540375 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 109013 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 495663 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 22243524 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 77757616 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 19856258 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 9307175 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 11163648 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 59419645 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 199110 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 2023904 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 235068 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 7176378 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 39704161 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 72277966 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 72138515 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 129817 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 34987460 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 4716693 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 1464722 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 211632 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 12540163 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 9262921 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 6150917 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1355884 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 997025 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 52994830 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 1876718 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 52216371 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 52644 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 6477091 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 2861227 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 1292062 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 140823886 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.370792 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.088351 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 119350315 84.75% 84.75% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 9307127 6.61% 91.36% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3871720 2.75% 94.11% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2724493 1.93% 96.04% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 2821208 2.00% 98.05% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 1374944 0.98% 99.02% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 898986 0.64% 99.66% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 361887 0.26% 99.92% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 113206 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 140823886 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 180499 18.19% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 1 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.19% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 473486 47.73% 65.92% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 338115 34.08% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 35829212 68.62% 68.62% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 56563 0.11% 68.73% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 28580 0.05% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 9526937 18.25% 87.04% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 5949680 11.39% 98.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 819736 1.57% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 52216371 # Type of FU issued
|
|
system.cpu0.iq.rate 0.355242 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 992101 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.019000 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 245730281 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 61098362 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 50826597 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 571091 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 267903 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 262355 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 52896880 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 307812 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 579556 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1070231 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 2809 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 17956 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 496898 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 18718 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 406168 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 495663 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 74229287 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 1063310 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 58247929 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 119878 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 9262921 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 6150917 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 1658630 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 39535 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 822687 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 17956 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 156887 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 351474 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 508361 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 51713827 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 9234499 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 502543 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 3376381 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 15134335 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 8213447 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 5899836 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.351823 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 51204042 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 51088952 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 26321891 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 36458900 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.347572 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.721961 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 6803374 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 584656 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 464905 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 139620670 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.367725 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.257359 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 121488072 87.01% 87.01% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 7189020 5.15% 92.16% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 3942453 2.82% 94.99% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 2051651 1.47% 96.46% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 1610967 1.15% 97.61% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 576073 0.41% 98.02% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 437348 0.31% 98.33% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 435843 0.31% 98.65% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1889243 1.35% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 139620670 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 51342045 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 51342045 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 13846709 # Number of memory references committed
|
|
system.cpu0.commit.loads 8192690 # Number of loads committed
|
|
system.cpu0.commit.membars 198882 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 7762297 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 259271 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 47551840 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 657143 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 2951360 5.75% 5.75% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 33433980 65.12% 70.87% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 55376 0.11% 70.98% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.98% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 28117 0.05% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 8391572 16.34% 87.38% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 5660021 11.02% 98.40% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 819736 1.60% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 51342045 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 1889243 # number cycles where commit BW limit reached
|
|
system.cpu0.rob.rob_reads 195675599 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 117488366 # The number of ROB writes
|
|
system.cpu0.timesIdled 519286 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 6164271 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 3696539134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 48394452 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 48394452 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 3.037294 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 3.037294 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.329240 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.329240 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 67992315 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 36972661 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 128885 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 130381 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 1712039 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 819549 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.replacements 1282830 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 506.258957 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 10531989 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 1283342 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 8.206689 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.258957 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988787 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.988787 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 56925383 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 56925383 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6490454 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6490454 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3680062 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 3680062 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162917 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 162917 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187619 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 187619 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 10170516 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 10170516 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 10170516 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 10170516 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 1594902 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 1594902 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1768783 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1768783 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20957 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 20957 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2842 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2842 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 3363685 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 3363685 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 3363685 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 3363685 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54779472000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 54779472000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 114120076576 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 388638000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 388638000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44723000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 44723000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 168899548576 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 168899548576 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8085356 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 8085356 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5448845 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 5448845 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183874 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 183874 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190461 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 190461 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 13534201 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 13534201 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 13534201 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 13534201 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197258 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.197258 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324616 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.324616 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113975 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113975 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014922 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014922 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248532 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.248532 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248532 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.248532 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 6977235 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 18493 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 119566 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 125 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.354674 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 147.944000 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 756224 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 756224 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579464 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 579464 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502811 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1502811 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5193 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5193 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082275 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 2082275 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082275 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 2082275 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015438 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 1015438 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265972 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 265972 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15764 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15764 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2841 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2841 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281410 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 1281410 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281410 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 1281410 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10125 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17170 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43462270000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43462270000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18192812239 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18192812239 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186019000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186019000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41882000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41882000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61655082239 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 61655082239 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61655082239 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 61655082239 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1482526500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1482526500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2174117500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2174117500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3656644000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3656644000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125590 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125590 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048813 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048813 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085733 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085733 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014916 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014916 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.094679 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.094679 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 909478 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 508.072720 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 7170024 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 909987 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 7.879260 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 42291813500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.072720 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992330 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.992330 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 9035950 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 9035950 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 7170024 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 7170024 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 7170024 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 7170024 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 7170024 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 7170024 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 955631 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 955631 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 955631 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 955631 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 955631 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 955631 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14538250986 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 14538250986 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 14538250986 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 14538250986 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 14538250986 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 14538250986 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 8125655 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 8125655 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 8125655 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 8125655 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 8125655 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 8125655 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117607 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.117607 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117607 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.117607 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117607 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.117607 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 15213.247567 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 15213.247567 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 8860 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 285 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 31.087719 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45336 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 45336 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 45336 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 45336 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 45336 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 45336 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 910295 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 910295 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 910295 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 910295 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 910295 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 910295 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12844771491 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12844771491 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12844771491 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 12844771491 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12844771491 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 12844771491 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112027 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.112027 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.112027 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 3566695 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 3123821 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 62988 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 1777720 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 839763 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 47.238204 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 169438 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 5003 # Number of incorrect RAS predictions.
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 1880373 # DTB read hits
|
|
system.cpu1.dtb.read_misses 9576 # DTB read misses
|
|
system.cpu1.dtb.read_acv 6 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 286028 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 1172828 # DTB write hits
|
|
system.cpu1.dtb.write_misses 2034 # DTB write misses
|
|
system.cpu1.dtb.write_acv 35 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 108538 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 3053201 # DTB hits
|
|
system.cpu1.dtb.data_misses 11610 # DTB misses
|
|
system.cpu1.dtb.data_acv 41 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 394566 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 516269 # ITB hits
|
|
system.cpu1.itb.fetch_misses 4737 # ITB misses
|
|
system.cpu1.itb.fetch_acv 64 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 521006 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numCycles 14959639 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 6140426 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 13703075 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 3566695 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 1009201 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 7602996 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 256204 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 312 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.MiscStallCycles 25106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 176452 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 62292 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 1530550 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 50498 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 14135722 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.969393 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.379564 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 11742806 83.07% 83.07% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 150793 1.07% 84.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 240174 1.70% 85.84% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 177797 1.26% 87.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 306821 2.17% 89.27% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 121463 0.86% 90.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 138409 0.98% 91.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 186182 1.32% 92.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 1071277 7.58% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 14135722 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.238421 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.916003 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 5035823 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 7049483 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 1732735 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 195750 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 121930 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 104865 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 6244 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 11127162 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 19879 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 121930 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 5174702 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 499846 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 5538858 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 1790125 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 1010259 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 10570144 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 4276 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 68050 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 20115 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.SQFullEvents 516529 # Number of times rename has blocked due to SQ full
|
|
system.cpu1.rename.RenamedOperands 6943229 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 12595828 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 12537363 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 52773 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 5938747 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 1004482 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 436817 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 40607 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 1800852 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 1926573 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 1243636 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 225182 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 130261 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 9311043 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 502453 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 9112092 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 20417 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 1494632 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 673391 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 369352 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 14135722 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.644615 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.367603 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 10331729 73.09% 73.09% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 1677616 11.87% 84.96% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 710014 5.02% 89.98% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 492260 3.48% 93.46% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 443396 3.14% 96.60% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 237464 1.68% 98.28% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 151784 1.07% 99.35% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 65612 0.46% 99.82% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 25847 0.18% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 14135722 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 23101 9.34% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.34% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 135152 54.66% 64.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 89008 36.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 5665609 62.18% 62.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 16110 0.18% 62.39% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 10836 0.12% 62.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 1960524 21.52% 84.05% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 1194738 13.11% 97.16% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 258998 2.84% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 9112092 # Type of FU issued
|
|
system.cpu1.iq.rate 0.609112 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 247261 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.027135 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 32423377 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 11214835 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 8782259 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 204207 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 97217 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 94699 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 9246642 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 109193 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 94025 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 261324 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 4031 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 123982 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 65647 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 121930 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 296920 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 166801 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 10329862 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 27466 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 1926573 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 1243636 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 455903 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 4091 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 161850 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 4031 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 28253 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 94223 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 122476 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 8997942 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 1896570 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 114150 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 516366 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 3077114 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 1335580 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 1180544 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.601481 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 8905860 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 8876958 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 4235192 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 6022422 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.593394 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.703237 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 1521482 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 133101 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 111980 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 13855601 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.631015 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.609308 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 10693520 77.18% 77.18% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 1462734 10.56% 87.74% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 528018 3.81% 91.55% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 318233 2.30% 93.84% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 242012 1.75% 95.59% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 100894 0.73% 96.32% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 90931 0.66% 96.97% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 102553 0.74% 97.71% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 316706 2.29% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 13855601 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 8743092 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 8743092 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 2784903 # Number of memory references committed
|
|
system.cpu1.commit.loads 1665249 # Number of loads committed
|
|
system.cpu1.commit.membars 42287 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 1247450 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 93039 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 8096711 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 139604 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 427747 4.89% 4.89% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 5200103 59.48% 64.37% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 15945 0.18% 64.55% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.55% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 10829 0.12% 64.68% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 1707536 19.53% 84.23% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 1120175 12.81% 97.04% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 258998 2.96% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 8743092 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 316706 # number cycles where commit BW limit reached
|
|
system.cpu1.rob.rob_reads 23719092 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 20805392 # The number of ROB writes
|
|
system.cpu1.timesIdled 122607 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 823917 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 3827854089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 8318863 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 8318863 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 1.798279 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 1.798279 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.556087 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.556087 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 11586341 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 6325577 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 52057 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 51356 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 501983 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 207801 # number of misc regfile writes
|
|
system.cpu1.dcache.tags.replacements 98586 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 486.617617 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 2459541 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 98896 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 24.869975 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 61777830500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.617617 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950425 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.950425 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 11508888 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 11508888 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 1514240 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 1514240 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 887339 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 887339 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 31145 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 31145 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29838 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 29838 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 2401579 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 2401579 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 2401579 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 2401579 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 186104 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 186104 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 193582 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 193582 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4934 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 4934 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2994 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 2994 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 379686 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 379686 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 379686 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 379686 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2502679500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 2502679500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9084892318 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 9084892318 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46731500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 46731500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48320000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 48320000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 11587571818 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 11587571818 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 11587571818 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 11587571818 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1700344 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 1700344 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1080921 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 1080921 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36079 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 36079 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32832 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 32832 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 2781265 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 2781265 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 2781265 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 2781265 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109451 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.109451 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179090 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.179090 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136755 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136755 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091192 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091192 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136516 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.136516 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136516 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.136516 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9471.321443 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9471.321443 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 537858 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 1114 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 16003 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.609823 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 123.777778 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 63787 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 63787 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 112960 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 112960 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 158580 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 158580 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 454 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 454 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 271540 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 271540 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 271540 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 271540 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73144 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 73144 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35002 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 35002 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4480 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4480 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2993 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 2993 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 108146 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 108146 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 108146 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 108146 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2930 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3080 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 925590000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 925590000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553309551 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1553309551 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37834000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37834000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45327000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45327000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2478899551 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 2478899551 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2478899551 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 2478899551 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 28469500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 28469500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 648479500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 648479500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676949000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676949000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043017 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043017 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032382 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032382 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124172 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124172 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091161 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091161 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.038884 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.038884 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8445.089286 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8445.089286 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 222828 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 467.348174 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 1300089 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 223338 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 5.821172 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 1895764140500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.348174 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912789 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.912789 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 1753949 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 1753949 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 1300089 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 1300089 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 1300089 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 1300089 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 1300089 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 1300089 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 230461 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 230461 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 230461 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 230461 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 230461 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 230461 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3280299500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 3280299500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 3280299500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 3280299500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 3280299500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 3280299500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 1530550 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 1530550 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 1530550 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 1530550 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 1530550 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 1530550 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150574 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.150574 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150574 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.150574 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150574 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.150574 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 14233.642569 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 14233.642569 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 780 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.571429 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7062 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 7062 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 7062 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 7062 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 7062 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 7062 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223399 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 223399 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 223399 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 223399 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 223399 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 223399 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2948315500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 2948315500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2948315500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 2948315500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2948315500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 2948315500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145960 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.145960 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.145960 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7371 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7371 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 54607 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 54607 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11900 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 40500 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 123956 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 73826 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2735458 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 11255000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 215099741 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 27445000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41696 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.507802 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1725999022000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 0.507802 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.031738 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.031738 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375552 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375552 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 176 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 176 # number of overall misses
|
|
system.iocache.overall_misses::total 176 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 22249883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 22249883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427997858 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 5427997858 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 22249883 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 22249883 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 22249883 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 22249883 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 126419.789773 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 126419.789773 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 126419.789773 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
|
system.iocache.writebacks::total 41520 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13449883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13449883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350397858 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 3350397858 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 13449883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 13449883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 13449883 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 13449883 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 76419.789773 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.446332 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.446332 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 344948 # number of replacements
|
|
system.l2c.tags.tagsinuse 65190.787367 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 3990905 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 410112 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 9.731256 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 11174884000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 53006.163408 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5332.464187 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 6575.010887 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 209.732945 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 67.415939 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.808810 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.081367 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.100327 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 1750 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 6246 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 5661 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 51290 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 38374495 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 38374495 # Number of data accesses
|
|
system.l2c.Writeback_hits::writebacks 820011 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 820011 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 181 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 256 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 437 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 155441 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 22735 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 178176 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 896343 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 221742 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1118085 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 736901 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 66152 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 803053 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 896343 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 892342 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 221742 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 88887 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2099314 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 896343 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 892342 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 221742 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 88887 # number of overall hits
|
|
system.l2c.overall_hits::total 2099314 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 2756 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1092 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 3848 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 412 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 449 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 114759 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 7322 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 122081 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 13662 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 1628 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 15290 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 272997 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 824 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 273821 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 13662 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 387756 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 1628 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 8146 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 411192 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 13662 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 387756 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 1628 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 8146 # number of overall misses
|
|
system.l2c.overall_misses::total 411192 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 3749500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 17004000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 20753500 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2598000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 405500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 3003500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 15999286000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1158590000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 17157876000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1831463500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 221176500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 2052640000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 33895753500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 116047500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 34011801000 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 1831463500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 49895039500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 221176500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1274637500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 53222317000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 1831463500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 49895039500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 221176500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1274637500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 53222317000 # number of overall miss cycles
|
|
system.l2c.Writeback_accesses::writebacks 820011 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 820011 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 2937 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1348 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 4285 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 461 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 475 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 936 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 270200 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 30057 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 300257 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 910005 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 223370 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1133375 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 1009898 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 66976 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 1076874 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 910005 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1280098 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 223370 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 97033 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2510506 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 910005 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1280098 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 223370 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 97033 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2510506 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938372 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.810089 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.898016 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.893709 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945263 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.919872 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.424719 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.243604 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.406588 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015013 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007288 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.013491 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.270321 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.012303 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.254274 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015013 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.302911 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.007288 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.083951 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.163788 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015013 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.302911 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.007288 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.083951 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.163788 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1360.486212 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15571.428571 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 5393.321206 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6305.825243 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 903.118040 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 3488.385598 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139416.394357 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 158234.089047 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 140545.015195 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 134055.299371 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135857.800983 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 134247.220405 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124161.633644 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140834.344660 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 124211.806253 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 134055.299371 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 128676.382828 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 135857.800983 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 156474.036337 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 129434.222942 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 134055.299371 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 128676.382828 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 135857.800983 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 156474.036337 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 129434.222942 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 81529 # number of writebacks
|
|
system.l2c.writebacks::total 81529 # number of writebacks
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 19 # number of ReadCleanReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 355 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 355 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2756 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1092 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 3848 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 412 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 449 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 114759 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 7322 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 122081 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13661 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1610 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 15271 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272997 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 824 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 273821 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 13661 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 387756 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 1610 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 8146 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 411173 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 13661 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 387756 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 1610 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 8146 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 411173 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 13055 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 20250 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 197825500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 78287000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 276112500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29369500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32234000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 61603500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14851696000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1085370000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 15937066000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1694708500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 202919000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 1897627500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31174991500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 107807500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 31282799000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 1694708500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 46026687500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 202919000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1193177500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 49117492500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 1694708500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 46026687500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 202919000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1193177500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 49117492500 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1394464000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 26594500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 1421058500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2057508000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 612939000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 2670447000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3451972000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 639533500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4091505500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938372 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.810089 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.898016 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.893709 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945263 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.919872 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424719 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.243604 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.406588 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013474 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270321 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012303 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254274 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 7195 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 296388 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 13055 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 13055 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 123049 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 262884 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 10279 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 5759 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 5112 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 122086 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 121678 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 289268 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 75 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40500 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187062 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1227712 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1352540 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73826 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31484224 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 31558050 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 34216290 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 11781 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 875308 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 875308 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 875308 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1356119148 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 92500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2187698407 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 69909650 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 5063061 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2531463 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 338644 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 1334 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 1266 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2238892 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 13055 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 13055 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 943078 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 1635745 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 10313 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 5834 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 16147 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 301580 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 301580 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1133694 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 1098094 # Transaction distribution
|
|
system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2554026 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3861302 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 573119 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 309440 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7297887 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58240320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130381048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 14295680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10315306 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 213232354 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 462162 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 5511701 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.123436 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.329209 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 4831850 87.67% 87.67% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 679365 12.33% 99.99% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 482 0.01% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 5511701 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 3368234918 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1366825726 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1954242307 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 335428339 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 167784154 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 6535 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 184475 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 65083 40.50% 40.50% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 131 0.08% 40.59% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1927 1.20% 41.79% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 93355 58.10% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 160682 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 64077 49.21% 49.21% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1927 1.48% 50.79% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 63891 49.07% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 130212 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1864797723000 97.04% 97.04% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 61900500 0.00% 97.04% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 553477500 0.03% 97.07% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::30 85562000 0.00% 97.07% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 56264153500 2.93% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1921762816500 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.984543 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.684388 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.810371 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 228 # number of syscalls executed
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 3533 2.09% 2.26% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 153850 90.93% 93.22% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6345 3.75% 96.97% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 4587 2.71% 99.69% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 169199 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 7137 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1347 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1346
|
|
system.cpu0.kern.mode_good::user 1347
|
|
system.cpu0.kern.mode_good::idle 0
|
|
system.cpu0.kern.mode_switch_good::kernel 0.188595 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.317421 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 1919561135500 99.89% 99.89% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 2201673000 0.11% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 3534 # number of times the context was actually changed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 55164 # number of hwrei instructions executed
|
|
system.cpu1.kern.ipl_count::0 17245 36.53% 36.53% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1925 4.08% 40.61% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 27750 58.79% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 47204 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 16874 47.30% 47.30% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1925 5.40% 52.70% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 284 0.80% 53.49% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 16590 46.51% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 35673 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1874997277000 97.58% 97.58% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 538569500 0.03% 97.61% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 135298500 0.01% 97.62% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 45735704500 2.38% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1921406849500 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.978487 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.597838 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::total 0.755720 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed
|
|
system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed
|
|
system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed
|
|
system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed
|
|
system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed
|
|
system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed
|
|
system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed
|
|
system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed
|
|
system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed
|
|
system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed
|
|
system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed
|
|
system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed
|
|
system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::total 98 # number of syscalls executed
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 1056 2.16% 2.55% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 42024 86.04% 88.61% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2414 4.94% 93.55% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 4 0.01% 93.56% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 2970 6.08% 99.65% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 48843 # number of callpals executed
|
|
system.cpu1.kern.mode_switch::kernel 1253 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 392 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2414 # number of protection mode switches
|
|
system.cpu1.kern.mode_good::kernel 600
|
|
system.cpu1.kern.mode_good::user 392
|
|
system.cpu1.kern.mode_good::idle 208
|
|
system.cpu1.kern.mode_switch_good::kernel 0.478851 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.086164 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 0.295639 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 4354098000 0.23% 0.23% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 702561000 0.04% 0.26% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1916032066000 99.74% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 1057 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
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