c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
216 lines
23 KiB
Plaintext
216 lines
23 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.395727 # Number of seconds simulated
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sim_ticks 395726778000 # Number of ticks simulated
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final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1695212 # Simulator instruction rate (inst/s)
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host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1047118075 # Simulator tick rate (ticks/s)
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host_mem_usage 304696 # Number of bytes of host memory used
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host_seconds 377.92 # Real time elapsed on the host
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sim_insts 640654410 # Number of instructions simulated
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sim_ops 788730069 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 2573511592 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
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system.physmem.bytes_read::total 3718230108 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 2573511592 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 2573511592 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
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system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 643377898 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 893713136 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 6503253596 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2892699154 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 9395952750 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 6503253596 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 6503253596 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1322421029 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1322421029 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s)
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system.membus.trans_dist::ReadReq 893703777 # Transaction distribution
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system.membus.trans_dist::ReadResp 893709516 # Transaction distribution
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system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
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system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
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system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
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system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
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system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
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system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
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system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
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system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram
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system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram
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system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 4 # Request fanout histogram
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system.membus.snoop_fanout::max_value 5 # Request fanout histogram
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system.membus.snoop_fanout::total 1022670352 # Request fanout histogram
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 673 # Number of system calls
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system.cpu.numCycles 791453557 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 640654410 # Number of instructions committed
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system.cpu.committedOps 788730069 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
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system.cpu.num_func_calls 37261296 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
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system.cpu.num_int_insts 682251400 # number of integer instructions
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system.cpu.num_fp_insts 24239771 # number of float instructions
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system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read
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system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 2369173291 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
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system.cpu.num_mem_refs 381221435 # number of memory refs
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system.cpu.num_load_insts 252240938 # Number of load instructions
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system.cpu.num_store_insts 128980497 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 791453557 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 137364859 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction
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system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
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system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
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system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 788730743 # Class of executed instruction
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---------- End Simulation Statistics ----------
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