1665 lines
190 KiB
Text
1665 lines
190 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000264 # Number of seconds simulated
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sim_ticks 263565500 # Number of ticks simulated
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final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 798172 # Simulator instruction rate (inst/s)
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host_op_rate 798158 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 317271660 # Simulator tick rate (ticks/s)
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host_mem_usage 306776 # Number of bytes of host memory used
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host_seconds 0.83 # Real time elapsed on the host
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sim_insts 663039 # Number of instructions simulated
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sim_ops 663039 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory
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system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 69204809 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 40065942 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 2428239 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 3642358 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 13112490 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 5342126 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 1214119 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 3885182 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 138895265 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 69204809 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 2428239 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 13112490 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 1214119 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 85959657 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 69204809 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 40065942 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 2428239 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 3642358 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 13112490 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 5342126 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 1214119 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 3885182 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 138895265 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.workload.num_syscalls 89 # Number of system calls
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system.cpu0.numCycles 527131 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 158196 # Number of instructions committed
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system.cpu0.committedOps 158196 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 108956 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu0.num_func_calls 390 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 25969 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 108956 # number of integer instructions
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system.cpu0.num_fp_insts 0 # number of float instructions
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system.cpu0.num_int_register_reads 315026 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 110562 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu0.num_mem_refs 73832 # number of memory refs
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system.cpu0.num_load_insts 48881 # Number of load instructions
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system.cpu0.num_store_insts 24951 # Number of store instructions
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system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
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system.cpu0.num_busy_cycles 527130.998000 # Number of busy cycles
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system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
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system.cpu0.Branches 26834 # Number of branches fetched
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system.cpu0.op_class::No_OpClass 23561 14.89% 14.89% # Class of executed instruction
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system.cpu0.op_class::IntAlu 60781 38.41% 53.29% # Class of executed instruction
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system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction
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system.cpu0.op_class::MemRead 48965 30.94% 84.23% # Class of executed instruction
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system.cpu0.op_class::MemWrite 24951 15.77% 100.00% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.op_class::total 158258 # Class of executed instruction
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system.cpu0.dcache.tags.replacements 2 # number of replacements
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system.cpu0.dcache.tags.tagsinuse 145.050771 # Cycle average of tags in use
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system.cpu0.dcache.tags.total_refs 73302 # Total number of references to valid blocks.
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system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.avg_refs 438.934132 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.050771 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283302 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_percent::total 0.283302 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
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system.cpu0.dcache.tags.tag_accesses 295559 # Number of tag accesses
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system.cpu0.dcache.tags.data_accesses 295559 # Number of data accesses
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system.cpu0.dcache.ReadReq_hits::cpu0.data 48703 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 48703 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 24717 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 24717 # number of WriteReq hits
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system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
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system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
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system.cpu0.dcache.demand_hits::cpu0.data 73420 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 73420 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 73420 # number of overall hits
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system.cpu0.dcache.overall_hits::total 73420 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
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system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
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system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
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system.cpu0.dcache.demand_misses::cpu0.data 351 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses
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system.cpu0.dcache.overall_misses::total 351 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4817500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::total 4817500 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6985500 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 6985500 # number of WriteReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu0.data 11803000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::total 11803000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu0.data 11803000 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::total 11803000 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 48871 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 48871 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::cpu0.data 24900 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 24900 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.demand_accesses::cpu0.data 73771 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 73771 # number of demand (read+write) accesses
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system.cpu0.dcache.overall_accesses::cpu0.data 73771 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 73771 # number of overall (read+write) accesses
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003438 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_miss_rate::total 0.003438 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007349 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::total 0.007349 # miss rate for WriteReq accesses
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system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004758 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total 0.004758 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004758 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.004758 # miss rate for overall accesses
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system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28675.595238 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total 28675.595238 # average ReadReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38172.131148 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total 38172.131148 # average WriteReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency
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system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::total 33626.780627 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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|
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
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|
system.cpu0.dcache.writebacks::total 1 # number of writebacks
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|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses
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system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses
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|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
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|
system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
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|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
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|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
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|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses
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|
system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses
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|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4649500 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4649500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6802500 # number of WriteReq MSHR miss cycles
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|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6802500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11452000 # number of demand (read+write) MSHR miss cycles
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|
system.cpu0.dcache.demand_mshr_miss_latency::total 11452000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11452000 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::total 11452000 # number of overall MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003438 # mshr miss rate for ReadReq accesses
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|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003438 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007349 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007349 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.004758 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.004758 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27675.595238 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27675.595238 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 215 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 337.884368 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.380247 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412852 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.412852 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 158726 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 158726 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 157792 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 157792 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 157792 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 157792 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 157792 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 157792 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 467 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20140500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 20140500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 20140500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 20140500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 20140500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 20140500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 158259 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 158259 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 158259 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 158259 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 158259 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 158259 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002951 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002951 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.002951 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002951 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.002951 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43127.408994 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 43127.408994 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 43127.408994 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 43127.408994 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 215 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19673500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 19673500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19673500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 19673500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19673500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 19673500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002951 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.002951 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.002951 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.numCycles 527130 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 170790 # Number of instructions committed
|
|
system.cpu1.committedOps 170790 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 110708 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 34050 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 110708 # number of integer instructions
|
|
system.cpu1.num_fp_insts 0 # number of float instructions
|
|
system.cpu1.num_int_register_reads 268858 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 101318 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 52827 # number of memory refs
|
|
system.cpu1.num_load_insts 41019 # Number of load instructions
|
|
system.cpu1.num_store_insts 11808 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 73818.861681 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 453311.138319 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.859961 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.140039 # Percentage of idle cycles
|
|
system.cpu1.Branches 35703 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 26483 15.50% 15.50% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 74610 43.68% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.18% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 57921 33.91% 93.09% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 11808 6.91% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 170822 # Class of executed instruction
|
|
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 26.474097 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 25884 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 892.551724 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.474097 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051707 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.051707 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 211529 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 211529 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 40844 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 40844 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 11631 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 11631 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 52475 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 52475 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 52475 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 52475 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 167 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 167 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 272 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 272 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 272 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 272 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1891500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 1891500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1642500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 1642500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 3534000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 3534000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 3534000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 3534000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 41011 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 41011 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 11736 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 11736 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 52747 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 52747 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 52747 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 52747 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004072 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.004072 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008947 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.008947 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005157 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.005157 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005157 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.005157 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11326.347305 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 11326.347305 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15642.857143 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 15642.857143 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 12992.647059 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1537500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1537500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3262000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 3262000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3262000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 3262000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004072 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004072 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008947 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008947 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.005157 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.005157 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10326.347305 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10326.347305 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 280 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 465.729508 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.953040 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130768 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.130768 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 171189 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 171189 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 170457 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 170457 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 170457 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 170457 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 170457 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 170457 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5688500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 5688500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 5688500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 5688500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 5688500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 5688500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 170823 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 170823 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 170823 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 170823 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 170823 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 170823 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002143 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.002143 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002143 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.002143 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002143 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.002143 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15542.349727 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 15542.349727 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 15542.349727 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 15542.349727 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.writebacks::writebacks 280 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 280 # number of writebacks
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5322500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5322500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5322500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 5322500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5322500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 5322500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.002143 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.numCycles 527130 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 168244 # Number of instructions committed
|
|
system.cpu2.committedOps 168244 # Number of ops (including micro ops) committed
|
|
system.cpu2.num_int_alu_accesses 109603 # Number of integer alu accesses
|
|
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu2.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu2.num_conditional_control_insts 33329 # number of instructions that are conditional controls
|
|
system.cpu2.num_int_insts 109603 # number of integer instructions
|
|
system.cpu2.num_fp_insts 0 # number of float instructions
|
|
system.cpu2.num_int_register_reads 267321 # number of times the integer registers were read
|
|
system.cpu2.num_int_register_writes 101101 # number of times the integer registers were written
|
|
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu2.num_mem_refs 52443 # number of memory refs
|
|
system.cpu2.num_load_insts 40463 # Number of load instructions
|
|
system.cpu2.num_store_insts 11980 # Number of store instructions
|
|
system.cpu2.num_idle_cycles 74087.861169 # Number of idle cycles
|
|
system.cpu2.num_busy_cycles 453042.138831 # Number of busy cycles
|
|
system.cpu2.not_idle_fraction 0.859450 # Percentage of non-idle cycles
|
|
system.cpu2.idle_fraction 0.140550 # Percentage of idle cycles
|
|
system.cpu2.Branches 34984 # Number of branches fetched
|
|
system.cpu2.op_class::No_OpClass 25761 15.31% 15.31% # Class of executed instruction
|
|
system.cpu2.op_class::IntAlu 74059 44.01% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::IntMult 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::IntDiv 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::FloatAdd 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::FloatCmp 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::FloatCvt 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::FloatMult 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::FloatDiv 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::FloatSqrt 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAdd 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAddAcc 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAlu 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdCmp 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdCvt 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMisc 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMult 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMultAcc 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdShift 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdSqrt 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMult 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.32% # Class of executed instruction
|
|
system.cpu2.op_class::MemRead 56476 33.56% 92.88% # Class of executed instruction
|
|
system.cpu2.op_class::MemWrite 11980 7.12% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::total 168276 # Class of executed instruction
|
|
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 27.444081 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 26343 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 878.100000 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.444081 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053602 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.053602 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
|
|
system.cpu2.dcache.tags.tag_accesses 209996 # Number of tag accesses
|
|
system.cpu2.dcache.tags.data_accesses 209996 # Number of data accesses
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 40285 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 40285 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 11801 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 11801 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 52086 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 52086 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 52086 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 52086 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 170 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 170 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 104 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 104 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 274 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2220000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 2220000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1703000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 1703000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 260000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 3923000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 3923000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 3923000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 3923000 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 40455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 40455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 11905 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 11905 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 52360 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 52360 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 52360 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 52360 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004202 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008736 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.008736 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005233 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.005233 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005233 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.005233 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13058.823529 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 13058.823529 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16375 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 16375 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.758621 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.758621 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 14317.518248 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2050000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2050000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1599000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1599000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3649000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 3649000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3649000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 3649000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004202 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004202 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008736 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008736 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.005233 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.005233 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12058.823529 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12058.823529 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15375 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15375 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.758621 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.758621 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.tags.replacements 280 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 458.773224 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.363893 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135476 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.135476 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu2.icache.tags.tag_accesses 168643 # Number of tag accesses
|
|
system.cpu2.icache.tags.data_accesses 168643 # Number of data accesses
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 167911 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 167911 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 167911 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 167911 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 167911 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 167911 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8088500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 8088500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 8088500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 8088500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 8088500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 8088500 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 168277 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 168277 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 168277 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 168277 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 168277 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 168277 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002175 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002175 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002175 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22099.726776 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 22099.726776 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 22099.726776 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 22099.726776 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.writebacks::writebacks 280 # number of writebacks
|
|
system.cpu2.icache.writebacks::total 280 # number of writebacks
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7722500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 7722500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7722500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 7722500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7722500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 7722500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.numCycles 527131 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.committedInsts 165809 # Number of instructions committed
|
|
system.cpu3.committedOps 165809 # Number of ops (including micro ops) committed
|
|
system.cpu3.num_int_alu_accesses 112442 # Number of integer alu accesses
|
|
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu3.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu3.num_conditional_control_insts 30690 # number of instructions that are conditional controls
|
|
system.cpu3.num_int_insts 112442 # number of integer instructions
|
|
system.cpu3.num_fp_insts 0 # number of float instructions
|
|
system.cpu3.num_int_register_reads 289238 # number of times the integer registers were read
|
|
system.cpu3.num_int_register_writes 110642 # number of times the integer registers were written
|
|
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu3.num_mem_refs 57921 # number of memory refs
|
|
system.cpu3.num_load_insts 41890 # Number of load instructions
|
|
system.cpu3.num_store_insts 16031 # Number of store instructions
|
|
system.cpu3.num_idle_cycles 74358.001718 # Number of idle cycles
|
|
system.cpu3.num_busy_cycles 452772.998282 # Number of busy cycles
|
|
system.cpu3.not_idle_fraction 0.858938 # Percentage of non-idle cycles
|
|
system.cpu3.idle_fraction 0.141062 # Percentage of idle cycles
|
|
system.cpu3.Branches 32344 # Number of branches fetched
|
|
system.cpu3.op_class::No_OpClass 23127 13.95% 13.95% # Class of executed instruction
|
|
system.cpu3.op_class::IntAlu 75479 45.51% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::IntMult 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::IntDiv 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::FloatAdd 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::FloatCmp 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::FloatCvt 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::FloatMult 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::FloatDiv 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::FloatSqrt 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAdd 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAddAcc 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAlu 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdCmp 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdCvt 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMisc 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMult 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMultAcc 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdShift 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdSqrt 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMult 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.46% # Class of executed instruction
|
|
system.cpu3.op_class::MemRead 51204 30.88% 90.33% # Class of executed instruction
|
|
system.cpu3.op_class::MemWrite 16031 9.67% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::total 165841 # Class of executed instruction
|
|
system.cpu3.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 25.704074 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 34341 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 1184.172414 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.704074 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050203 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.050203 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu3.dcache.tags.tag_accesses 231895 # Number of tag accesses
|
|
system.cpu3.dcache.tags.data_accesses 231895 # Number of data accesses
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 41733 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 41733 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 15853 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 15853 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 57586 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 57586 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 57586 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 57586 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 150 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 150 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 259 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1542500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 1542500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1810500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 1810500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 250500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 250500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 3353000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 3353000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 3353000 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 3353000 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 41883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 41883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 15962 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 15962 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 57845 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 57845 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 57845 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 57845 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003581 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.003581 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006829 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.006829 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004477 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.004477 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004477 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.004477 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 10283.333333 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 10283.333333 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16610.091743 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 16610.091743 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4473.214286 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 4473.214286 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 12945.945946 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 259 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 259 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1392500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1392500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1701500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1701500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 194500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 194500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3094000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 3094000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3094000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 3094000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003581 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006829 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006829 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.004477 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.004477 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9283.333333 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9283.333333 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3473.214286 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3473.214286 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.tags.replacements 281 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 450.885559 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.942208 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126840 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.126840 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu3.icache.tags.tag_accesses 166209 # Number of tag accesses
|
|
system.cpu3.icache.tags.data_accesses 166209 # Number of data accesses
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 165475 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 165475 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 165475 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 165475 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 165475 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 165475 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 367 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5473500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 5473500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 165842 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 165842 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 165842 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 165842 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 165842 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 165842 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002213 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.002213 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002213 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.002213 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002213 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.002213 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 14914.168937 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.writebacks::writebacks 281 # number of writebacks
|
|
system.cpu3.icache.writebacks::total 281 # number of writebacks
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5106500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 5106500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002213 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.002213 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.002213 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 347.185045 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1714 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 0.881447 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 230.714883 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 54.006864 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 6.227742 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 0.835119 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 46.668024 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 6.066881 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 0.961095 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 0.822991 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.003520 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.005298 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 19669 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 19669 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1218 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 301 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 3 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
|
system.l2c.overall_hits::total 1218 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 14 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 594 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 65 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 23 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 10 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 16 # number of overall misses
|
|
system.l2c.overall_misses::total 594 # number of overall misses
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5892000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 837500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 905000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 836000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 8470500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 16965000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 831500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3806500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 555500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 22158500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 3927500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 118000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 475500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu3.data 119000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 4640000 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 16965000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 9819500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 831500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 955500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 3806500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1380500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 555500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 955000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 35269000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 16965000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 9819500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 831500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 955500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 3806500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1380500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 555500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 955000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 35269000 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 14 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.177596 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.027248 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59515.151515 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 59821.428571 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60333.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 59714.285714 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 59651.408451 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59526.315789 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59392.857143 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58561.538462 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55550 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 59247.326203 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59507.575758 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59000 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59437.500000 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 59487.179487 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 59526.315789 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 59392.857143 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 59718.750000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 58561.538462 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 60021.739130 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 55550 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 59375.420875 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 59526.315789 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 59392.857143 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 59718.750000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 58561.538462 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 60021.739130 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 55550 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 59375.420875 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 11 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 5 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 11 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 5 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 22 # number of overall MSHR hits
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 14 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 14 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 54 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 7 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 54 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 22 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 54 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 22 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 533000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 271000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 269000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 381000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 1454000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4902000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 697500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 755000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 696000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 7050500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 14115000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 500500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2674000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 247500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 17537000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 3267500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 49500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 346500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 99000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 3762500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 14115000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 8169500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 500500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 747000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 2674000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 1101500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 247500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 795000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 28350000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 14115000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 8169500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 500500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 747000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 2674000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 1101500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 247500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 795000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 28350000 # number of overall MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.013624 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.636364 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013624 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013624 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19035.714286 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19357.142857 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19214.285714 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19050 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19131.578947 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49821.428571 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50333.333333 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49714.285714 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 49651.408451 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50050 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49500 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49539.548023 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadResp 430 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 271 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1481 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1481 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 261 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 915 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 915 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 685132 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 3976 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 1120 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1854 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 424 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 424 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1028 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 2918 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.265250 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 1.153418 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 1002 34.34% 34.34% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 794 27.21% 61.55% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 468 16.04% 77.59% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 654 22.41% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 2918 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 3048992 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 500989 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 435970 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 554485 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 441968 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 552992 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 411482 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|