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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
Steve Reinhardt d7c083864c stats: update stats for ld.so support 
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
2016-03-17 10:32:53 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.767851 # Number of seconds simulated
sim_ticks 767851412000 # Number of ticks simulated
final_tick 767851412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 96147 # Simulator instruction rate (inst/s)
host_op_rate 103584 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47797800 # Simulator tick rate (ticks/s)
host_mem_usage 342312 # Number of bytes of host memory used
host_seconds 16064.58 # Real time elapsed on the host
sim_insts 1544563024 # Number of instructions simulated
sim_ops 1664032416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 235334976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 63685504 # Number of bytes read from this memory
system.physmem.bytes_read::total 299085440 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 104625984 # Number of bytes written to this memory
system.physmem.bytes_written::total 104625984 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3677109 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 995086 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4673210 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1634781 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1634781 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 84600 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 306485047 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 82939880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 389509527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 84600 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 84600 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 136258112 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 136258112 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 136258112 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 84600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 306485047 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 82939880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 525767639 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4673210 # Number of read requests accepted
system.physmem.writeReqs 1634781 # Number of write requests accepted
system.physmem.readBursts 4673210 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1634781 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 298595648 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 489792 # Total number of bytes read from write queue
system.physmem.bytesWritten 104623680 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 299085440 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 104625984 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 7653 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 301092 # Per bank write bursts
system.physmem.perBankRdBursts::1 298585 # Per bank write bursts
system.physmem.perBankRdBursts::2 284412 # Per bank write bursts
system.physmem.perBankRdBursts::3 287553 # Per bank write bursts
system.physmem.perBankRdBursts::4 288019 # Per bank write bursts
system.physmem.perBankRdBursts::5 285340 # Per bank write bursts
system.physmem.perBankRdBursts::6 281024 # Per bank write bursts
system.physmem.perBankRdBursts::7 277791 # Per bank write bursts
system.physmem.perBankRdBursts::8 293545 # Per bank write bursts
system.physmem.perBankRdBursts::9 299289 # Per bank write bursts
system.physmem.perBankRdBursts::10 291195 # Per bank write bursts
system.physmem.perBankRdBursts::11 297241 # Per bank write bursts
system.physmem.perBankRdBursts::12 298946 # Per bank write bursts
system.physmem.perBankRdBursts::13 298565 # Per bank write bursts
system.physmem.perBankRdBursts::14 293948 # Per bank write bursts
system.physmem.perBankRdBursts::15 289012 # Per bank write bursts
system.physmem.perBankWrBursts::0 103815 # Per bank write bursts
system.physmem.perBankWrBursts::1 101663 # Per bank write bursts
system.physmem.perBankWrBursts::2 99081 # Per bank write bursts
system.physmem.perBankWrBursts::3 99729 # Per bank write bursts
system.physmem.perBankWrBursts::4 98947 # Per bank write bursts
system.physmem.perBankWrBursts::5 98825 # Per bank write bursts
system.physmem.perBankWrBursts::6 102537 # Per bank write bursts
system.physmem.perBankWrBursts::7 104314 # Per bank write bursts
system.physmem.perBankWrBursts::8 105187 # Per bank write bursts
system.physmem.perBankWrBursts::9 104412 # Per bank write bursts
system.physmem.perBankWrBursts::10 101681 # Per bank write bursts
system.physmem.perBankWrBursts::11 102588 # Per bank write bursts
system.physmem.perBankWrBursts::12 102740 # Per bank write bursts
system.physmem.perBankWrBursts::13 102708 # Per bank write bursts
system.physmem.perBankWrBursts::14 104126 # Per bank write bursts
system.physmem.perBankWrBursts::15 102392 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 767851370500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 4673210 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1634781 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 2763298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1028318 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 325143 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 231238 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 149204 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 81551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 37590 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 23700 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 18069 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 4228 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1700 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 25895 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 28601 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 56060 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 73237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 85035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 93837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 99991 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 103634 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 105624 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 106179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 107211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 108036 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 109230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 110922 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 111311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 103575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 100806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 100214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2991 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 586 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 4241219 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 95.071143 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 78.963204 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 102.762534 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 3377855 79.64% 79.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 665363 15.69% 95.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 95455 2.25% 97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 35191 0.83% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 22820 0.54% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12430 0.29% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7284 0.17% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5212 0.12% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19609 0.46% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 4241219 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 97672 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 47.767497 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 100.584321 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255 95276 97.55% 97.55% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511 1151 1.18% 98.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-767 710 0.73% 99.45% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-1023 401 0.41% 99.86% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-4863 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 97672 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 97672 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.737089 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.693249 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.262570 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 68211 69.84% 69.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 2039 2.09% 71.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 18248 18.68% 90.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 5781 5.92% 96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 2040 2.09% 98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 736 0.75% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 303 0.31% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 177 0.18% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 71 0.07% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 35 0.04% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 22 0.02% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 97672 # Writes before turning the bus around for reads
system.physmem.totQLat 128403949042 # Total ticks spent queuing
system.physmem.totMemAccLat 215883142792 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 23327785000 # Total ticks spent in databus transfers
system.physmem.avgQLat 27521.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 46271.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 388.87 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 136.26 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 389.51 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 136.26 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 4.10 # Data bus utilization in percentage
system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing
system.physmem.readRowHits 1711348 # Number of row buffer hits during reads
system.physmem.writeRowHits 347723 # Number of row buffer hits during writes
system.physmem.readRowHitRate 36.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 21.27 # Row buffer hit rate for writes
system.physmem.avgGap 121726.77 # Average gap between requests
system.physmem.pageHitRate 32.68 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 15936283440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 8695392750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 17969468400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 5241691440 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 414929915685 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 96735845250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 609660749925 # Total energy per rank (pJ)
system.physmem_0.averagePower 793.985115 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 158402074288 # Time in different power states
system.physmem_0.memoryStateTime::REF 25640160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 583806871462 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 16127249040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 8799590250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 18421525200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 5351352480 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 410152468095 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 100926587250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 609930925275 # Total energy per rank (pJ)
system.physmem_1.averagePower 794.336977 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 165409997970 # Time in different power states
system.physmem_1.memoryStateTime::REF 25640160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 576799157530 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 286283871 # Number of BP lookups
system.cpu.branchPred.condPredicted 223409198 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14630000 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 157660833 # Number of BTB lookups
system.cpu.branchPred.BTBHits 150354422 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 95.365741 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16641462 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1535702825 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 13928194 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2067545272 # Number of instructions fetch has processed
system.cpu.fetch.Branches 286283871 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 166995884 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1507053814 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29284843 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 194 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 878 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 656961352 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 924 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1535625501 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.442414 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.228162 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 453179554 29.51% 29.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 465452437 30.31% 59.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 101425758 6.60% 66.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 515567752 33.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1535625501 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.186419 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.346319 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 74705832 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 538167437 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 849914387 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 58196125 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 14641720 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 42203366 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 738 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2037249572 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 52491206 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 14641720 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 139798655 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 457197163 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 837846796 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 86126990 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1976444651 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 26741715 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 45304447 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 126733 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1592000 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 25068959 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 1985917884 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 9128448478 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2432959376 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 311018939 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 156 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 147 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 111499439 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 542575800 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 199311764 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 26984794 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 29485637 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1948029914 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 213 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1857440521 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13485383 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 283997711 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 647527066 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1535625501 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.209566 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.150575 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 582643896 37.94% 37.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 326148429 21.24% 59.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 378192784 24.63% 83.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 219661214 14.30% 98.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 28973008 1.89% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 6170 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1535625501 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 166041601 41.02% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 1966 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 191453028 47.29% 88.31% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 47322574 11.69% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1138257310 61.28% 61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 800951 0.04% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 532072663 28.65% 89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 186309545 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1857440521 # Type of FU issued
system.cpu.iq.rate 1.209505 # Inst issue rate
system.cpu.iq.fu_busy_cnt 404819169 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.217945 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5668810855 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2232040657 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1805715757 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2262259556 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 17798811 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 84269466 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 66606 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13290 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 24464719 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4470256 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4868274 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 14641720 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 25371637 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1306573 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1948030205 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 542575800 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 199311764 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 151 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 159252 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1145955 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13290 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 7700252 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8704527 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 16404779 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1827784428 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 516894749 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29656093 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 78 # number of nop insts executed
system.cpu.iew.exec_refs 698647521 # number of memory reference insts executed
system.cpu.iew.exec_branches 229543891 # Number of branches executed
system.cpu.iew.exec_stores 181752772 # Number of stores executed
system.cpu.iew.exec_rate 1.190194 # Inst execution rate
system.cpu.iew.wb_sent 1808752237 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1805715827 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1169206310 # num instructions producing a value
system.cpu.iew.wb_consumers 1689633446 # num instructions consuming a value
system.cpu.iew.wb_rate 1.175824 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.691988 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 258099424 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 14629299 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1496131949 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.112223 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.027889 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 915820639 61.21% 61.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 250646763 16.75% 77.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 110056209 7.36% 85.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 55261288 3.69% 89.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 29350080 1.96% 90.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 34099698 2.28% 93.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 24719772 1.65% 94.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 18148053 1.21% 96.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 58029447 3.88% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1496131949 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 633153379 # Number of memory references committed
system.cpu.commit.loads 458306334 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462427 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
system.cpu.commit.bw_lim_events 58029447 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3360233761 # The number of ROB reads
system.cpu.rob.rob_writes 3883762364 # The number of ROB writes
system.cpu.timesIdled 834 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 77324 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.994264 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.994264 # CPI: Total CPI of All Threads
system.cpu.ipc 1.005769 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.005769 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2175773439 # number of integer regfile reads
system.cpu.int_regfile_writes 1261589366 # number of integer regfile writes
system.cpu.fp_regfile_reads 40 # number of floating regfile reads
system.cpu.fp_regfile_writes 52 # number of floating regfile writes
system.cpu.cc_regfile_reads 6965635020 # number of cc regfile reads
system.cpu.cc_regfile_writes 551858996 # number of cc regfile writes
system.cpu.misc_regfile_reads 675848866 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.dcache.tags.replacements 17003597 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.964807 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 638080633 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 17004109 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.525085 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.964807 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1335734207 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1335734207 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 469362265 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 469362265 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 168718228 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 168718228 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 638080493 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 638080493 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 638080493 # number of overall hits
system.cpu.dcache.overall_hits::total 638080493 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 17416613 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 17416613 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3867819 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3867819 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 21284432 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 21284432 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21284434 # number of overall misses
system.cpu.dcache.overall_misses::total 21284434 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 412110560500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 412110560500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 148910053049 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 148910053049 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 561020613549 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 561020613549 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 561020613549 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 561020613549 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 486778878 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 486778878 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 659364925 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 659364925 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 659364927 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 659364927 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022411 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.022411 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23661.923274 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 23661.923274 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38499.747028 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38499.747028 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26358.260984 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26358.260984 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26358.258507 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26358.258507 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 20478587 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3417945 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 942442 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 67202 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.729281 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50.860763 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 17003597 # number of writebacks
system.cpu.dcache.writebacks::total 17003597 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150032 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3150032 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130287 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1130287 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4280319 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4280319 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4280319 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4280319 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266581 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 14266581 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737532 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2737532 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 17004113 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 17004113 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 17004114 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 17004114 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331850986000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 331850986000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115586978404 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 115586978404 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447437964404 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 447437964404 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447438032404 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 447438032404 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23260.722804 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23260.722804 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42223.060189 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42223.060189 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26313.513937 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26313.513937 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26313.516388 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26313.516388 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 586 # number of replacements
system.cpu.icache.tags.tagsinuse 444.620453 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 656959766 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1072 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 612835.602612 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 444.620453 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.868399 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.868399 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1313923770 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1313923770 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 656959766 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 656959766 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 656959766 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 656959766 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 656959766 # number of overall hits
system.cpu.icache.overall_hits::total 656959766 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1583 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1583 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1583 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1583 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1583 # number of overall misses
system.cpu.icache.overall_misses::total 1583 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 101448987 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 101448987 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 101448987 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 101448987 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 101448987 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 101448987 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 656961349 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 656961349 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 656961349 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 656961349 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 656961349 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 656961349 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64086.536323 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 64086.536323 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 64086.536323 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 64086.536323 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 16918 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 173 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 89.513228 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 34.600000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 586 # number of writebacks
system.cpu.icache.writebacks::total 586 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 509 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 509 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 509 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 509 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 509 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1074 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1074 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1074 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1074 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1074 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74582990 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 74582990 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74582990 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 74582990 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74582990 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 74582990 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69444.124767 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69444.124767 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 11607728 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 11635838 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 19050 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 5 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4655842 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 4705864 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16099.842459 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 22826032 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4721788 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.834192 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 54104143500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 13102.285184 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 2.119304 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2995.437971 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.799700 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000129 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182827 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.982656 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 773 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15151 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 599 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 172 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2950 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4343 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5551 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1838 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.047180 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.924744 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 552240776 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 552240776 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 4834377 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 4834377 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 12148517 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 12148517 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1758217 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1758217 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520794 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 11520794 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 13279011 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13279068 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 13279011 # number of overall hits
system.cpu.l2cache.overall_hits::total 13279068 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 979355 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 979355 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1017 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1017 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745743 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 2745743 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3725098 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3726115 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3725098 # number of overall misses
system.cpu.l2cache.overall_misses::total 3726115 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 100500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 100500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98934121000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 98934121000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73094500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 73094500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234186702000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 234186702000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 73094500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 333120823000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 333193917500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 73094500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 333120823000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 333193917500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 4834377 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 4834377 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 12148517 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 12148517 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737572 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2737572 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1074 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266537 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 14266537 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1074 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 17004109 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 17005183 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1074 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 17004109 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 17005183 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357746 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.357746 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946927 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946927 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192460 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192460 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946927 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.219070 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.219116 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946927 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.219070 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.219116 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20100 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20100 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101019.672131 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101019.672131 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71872.664700 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71872.664700 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85290.830934 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85290.830934 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89421.265178 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89421.265178 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1634781 # number of writebacks
system.cpu.l2cache.writebacks::total 1634781 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3953 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 3953 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45302 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45302 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 49255 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 49256 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 49255 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 49256 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 1144188 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975402 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1016 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1016 # number of ReadCleanReq MSHR misses
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system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700441 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1016 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3675843 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 1016 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3675843 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 4821047 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72422793987 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92707545500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92707545500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66931500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66931500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215168959000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215168959000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66931500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307876504500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 307943436000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66931500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307876504500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 380366229987 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356302 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356302 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.945996 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189285 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189285 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216220 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.283505 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63296.236271 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95045.474071 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95045.474071 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65877.460630 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65877.460630 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79679.192769 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79679.192769 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83751.766385 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78897.017595 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 34009371 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004197 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2918881 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2900097 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18784 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 14267609 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 6469158 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 12169806 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 5772538 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 1435459 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2737572 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2737572 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1074 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266537 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2732 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011834 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 51014566 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176493760 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2176599872 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 8842787 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 25847966 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.114476 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.320662 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 22907787 88.63% 88.63% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2921395 11.30% 99.93% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 18784 0.07% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 25847966 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 34008868522 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 13530 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1609497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 25506170491 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3697667 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1634781 # Transaction distribution
system.membus.trans_dist::CleanEvict 3002759 # Transaction distribution
system.membus.trans_dist::UpgradeReq 5 # Transaction distribution
system.membus.trans_dist::ReadExReq 975542 # Transaction distribution
system.membus.trans_dist::ReadExResp 975542 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3697668 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983964 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13983964 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403711360 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 403711360 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 9310755 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 9310755 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 9310755 # Request fanout histogram
system.membus.reqLayer0.occupancy 17653458992 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 25411663187 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
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