89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
422 lines
44 KiB
Text
422 lines
44 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 8039250 # Number of BTB hits
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global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
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global.BPredUnit.lookups 16249463 # Number of BP lookups
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global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
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host_inst_rate 207814 # Simulator instruction rate (inst/s)
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host_mem_usage 214944 # Number of bytes of host memory used
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host_seconds 382.99 # Real time elapsed on the host
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host_tick_rate 70849023 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 79591756 # Number of instructions simulated
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sim_seconds 0.027135 # Number of seconds simulated
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sim_ticks 27134794500 # Number of ticks simulated
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system.cpu.commit.COM:branches 13754477 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 51751168
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 22506445 4348.97%
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1 11357579 2194.65%
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2 5114502 988.29%
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3 3560855 688.07%
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4 2552504 493.23%
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5 1532717 296.17%
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6 1008933 194.96%
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7 796739 153.96%
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8 3320894 641.70%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 88340672 # Number of instructions committed
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system.cpu.commit.COM:loads 20379399 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 35224018 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 79591756 # Number of Instructions Simulated
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system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
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system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 33838925 # number of overall hits
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system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1199965 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 200933 # number of replacements
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system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use
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system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 147760 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 36599689 # DTB accesses
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system.cpu.dtb.acv 39 # DTB access violations
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system.cpu.dtb.hits 36425481 # DTB hits
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system.cpu.dtb.misses 174208 # DTB misses
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system.cpu.dtb.read_accesses 21541288 # DTB read accesses
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system.cpu.dtb.read_acv 37 # DTB read access violations
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system.cpu.dtb.read_hits 21383020 # DTB read hits
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system.cpu.dtb.read_misses 158268 # DTB read misses
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system.cpu.dtb.write_accesses 15058401 # DTB write accesses
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system.cpu.dtb.write_acv 2 # DTB write access violations
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system.cpu.dtb.write_hits 15042461 # DTB write hits
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system.cpu.dtb.write_misses 15940 # DTB write misses
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system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched
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system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 53041270
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system.cpu.fetch.rateDist.min_value 0
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0 33206277 6260.46%
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1 1871594 352.86%
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2 1529415 288.34%
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3 1809626 341.17%
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4 3985239 751.35%
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5 1867239 352.04%
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6 695846 131.19%
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7 1111736 209.60%
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8 6964298 1313.00%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
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system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses
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system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 13297366 # number of overall hits
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system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses
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system.cpu.icache.overall_misses 88706 # number of overall misses
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system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 83888 # number of replacements
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system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use
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system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 14745486 # Number of branches executed
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system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed
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system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate
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system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 15291392 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value
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system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 32396987 # num instructions producing a value
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system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle
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system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations
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system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed
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system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed
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system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations
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system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly
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system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle
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system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads
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system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0.start_dist
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No_OpClass 0 0.00% # Type of FU issued
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IntAlu 47898565 56.12% # Type of FU issued
|
|
IntMult 42953 0.05% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 121655 0.14% # Type of FU issued
|
|
FloatCmp 88 0.00% # Type of FU issued
|
|
FloatCvt 122104 0.14% # Type of FU issued
|
|
FloatMult 53 0.00% # Type of FU issued
|
|
FloatDiv 38535 0.05% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 21753622 25.49% # Type of FU issued
|
|
MemWrite 15368770 18.01% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 97100 9.91% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 470602 48.04% # attempts to use FU when none available
|
|
MemWrite 411938 42.05% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 17563410 3311.27%
|
|
1 13937999 2627.76%
|
|
2 8266125 1558.43%
|
|
3 4784809 902.09%
|
|
4 4627568 872.45%
|
|
5 2066740 389.65%
|
|
6 1112374 209.72%
|
|
7 454507 85.69%
|
|
8 227738 42.94%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 13412237 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 13386072 # ITB hits
|
|
system.cpu.itb.misses 26165 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 102894 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 188071 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 148779 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 120647 # number of writebacks
|
|
system.cpu.numCycles 54269590 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|