Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
90 lines
1.4 KiB
INI
90 lines
1.4 KiB
INI
[root]
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type=Root
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children=system
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dummy=0
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=AtomicSimpleCPU
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children=dtb itb tracer workload
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checker=Null
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clock=500
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cpu_id=0
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defer_registration=false
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do_checkpoint_insts=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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progress_interval=0
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simulate_data_stalls=false
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simulate_inst_stalls=false
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system=system
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tracer=system.cpu.tracer
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width=1
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workload=system.cpu.workload
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dcache_port=system.membus.port[2]
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icache_port=system.membus.port[1]
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[system.cpu.dtb]
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type=SparcDTB
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size=64
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[system.cpu.itb]
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type=SparcITB
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size=64
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[system.cpu.tracer]
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type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=0
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system=system
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uid=100
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[system.membus]
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type=Bus
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block_size=64
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bus_id=0
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clock=1000
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header_cycles=1
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responder_set=false
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width=64
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port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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