3d93afe348
Regression tester updates required by the following patches: brad/moved_python_protocol_files: config: moved python protocol config files brad/ruby_options_movement: config: reorganized how ruby specifies command-line options brad/config_token_bcast: ruby: added token broadcast config params to cmd options brad/topology_name: config: Added the topology description to m5 config.ini brad/ruby_system_names: config: Improve ruby simobject names brad/consolidated_protocol_stats: slicc: Consolidated the protocol stats printing brad/ruby_request_type_ostream_fix: ruby: Added ruby_request_type ostream def to libruby.hh brad/memtest_dma_extension: memtest: Memtester support for DMA brad/token_dma_lockdown_fix: MOESI_CMP_token: Fixed dma persistent lockdown bugs brad/profile_generic_mach_type: ruby: Reincarnated the responding machine profiling brad/network_msg_consolidated_stats: ruby: Added consolidated network msg stats brad/bcast_msg_profiling: ruby: Added bcast msg profiling to hammer and token brad/l2cache_profiling_fix: ruby: Fixed L2 cache miss profiling brad/llsc_ruby_m5_fix: ruby: fix ruby llsc support to sync sc outcomes brad/ruby_latency_fixes: ruby: Reduced ruby latencies brad/hammer_l2_cache_latency: ruby: Updated MOESI_hammer L2 latency behavior brad/deterministic_resurrection: ruby: Resurrected Ruby's deterministic tests brad/token_dma_fixes: ruby: MOESI_CMP_token dma fixes brad/ruby_cmd_options: config: added cmd options to control ruby debug brad/token_owner_fixes: ruby: fixed token bugs associated with owner token counts brad/ruby_remove_try_except: ruby: Improved try except blocks in ruby creation brad/ruby_port_callback_fix: ruby: Fixed RubyPort sendTiming callbacks brad/interrupt_drain_fix: devices: Fixed periodic interrupts to work with draining brad/llsc_trace_profile: ruby: Added SC fail indication to trace profiling brad/no_migrate_atomic: ruby: Disable migratory sharing for token and hammer brad/ruby_start_time_fix: ruby: Reset ruby stats in RubySystem unserialize brad/numa_bit_select_fix: ruby: fixed DirectoryMemory's numa_high_bit configuration brad/hammer_probe_filter: ruby: added probe filter support to hammer brad/miss_latency_detail_profile: MOESI_hammer: break down miss latency stalled cycles brad/recycle_latency_fix: ruby: Recycle latency fix for hammer brad/stall_and_wait: ruby: Stall and wait input messages instead of recycling brad/rubytest_request_flag_fix: ruby: Fixed minor bug in ruby test for setting the request type brad/hammer_merge_gets: ruby: Added merge GETS optimization to hammer brad/regress_updates: regress: Regression tester updates
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 1234
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randomization: 1
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cycle_period: 1
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block_size_bytes: 64
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block_size_bits: 6
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memory_size_bytes: 134217728
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memory_size_bits: 27
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology: Crossbar
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virtual_net_0: active, ordered
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virtual_net_1: active, ordered
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virtual_net_2: active, unordered
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virtual_net_3: active, unordered
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virtual_net_4: active, unordered
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virtual_net_5: active, unordered
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virtual_net_6: inactive
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virtual_net_7: inactive
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virtual_net_8: inactive
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virtual_net_9: inactive
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Profiler Configuration
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----------------------
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periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Aug/05/2010 14:46:32
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 0.69
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Virtual_time_in_minutes: 0.0115
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Virtual_time_in_hours: 0.000191667
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Virtual_time_in_days: 7.98611e-06
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Ruby_current_time: 213851
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Ruby_start_time: 0
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Ruby_cycles: 213851
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mbytes_resident: 31.293
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mbytes_total: 31.3008
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resident_ratio: 1
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ruby_cycles_executed: [ 213852 ]
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Busy Controller Counts:
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L1Cache-0:0
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Directory-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 16 count: 963 average: 15.8069 | standard deviation: 1.15034 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 65 883 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 128 max: 23081 count: 948 average: 3529.13 | standard deviation: 5116.76 | 71 12 47 82 73 59 68 59 47 38 28 25 17 14 12 7 10 4 1 9 4 5 5 7 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 4 4 5 5 1 4 3 3 3 3 3 3 4 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 8 max: 1215 count: 59 average: 478.39 | standard deviation: 246.067 | 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 128 max: 15642 count: 41 average: 3000.32 | standard deviation: 4886.74 | 5 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 128 max: 23081 count: 848 average: 3766.95 | standard deviation: 5236.59 | 61 10 32 62 58 52 60 56 43 35 27 24 17 14 12 5 10 4 0 9 4 5 5 6 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 4 3 4 4 1 4 3 3 3 3 3 3 4 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_L1Cache: [binsize: 1 max: 118 count: 65 average: 15.8923 | standard deviation: 35.394 | 0 9 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
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miss_latency_L2Cache: [binsize: 128 max: 19544 count: 29 average: 3519.03 | standard deviation: 5619.12 | 6 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Directory: [binsize: 128 max: 23081 count: 854 average: 3796.87 | standard deviation: 5197.84 | 0 10 46 78 72 57 67 59 47 38 27 25 16 14 12 7 10 3 1 9 4 5 5 6 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 3 4 5 4 1 4 3 3 3 3 3 3 3 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 854
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miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average: 2.5 | standard deviation: 1 | 0 0 1 1 ]
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miss_latency_IFETCH_L2Cache: [binsize: 1 max: 123 count: 3 average: 50 | standard deviation: 63.2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_IFETCH_Directory: [binsize: 8 max: 1215 count: 54 average: 519.815 | standard deviation: 213.139 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 5 average: 3 | standard deviation: 0.707107 | 0 0 1 3 1 ]
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miss_latency_LD_Directory: [binsize: 128 max: 15642 count: 36 average: 3416.61 | standard deviation: 5082.33 | 0 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 58 average: 17.4655 | standard deviation: 37.1906 | 0 9 12 12 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
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miss_latency_ST_L2Cache: [binsize: 128 max: 19544 count: 26 average: 3919.31 | standard deviation: 5809.69 | 3 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_Directory: [binsize: 128 max: 23081 count: 764 average: 4046.41 | standard deviation: 5309.16 | 0 8 31 58 57 50 59 56 43 35 26 24 16 14 12 5 10 3 0 9 4 5 5 5 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 3 3 4 3 1 4 3 3 3 3 3 3 3 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 6929
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page_faults: 1882
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swaps: 0
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block_inputs: 0
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block_outputs: 0
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Network Stats
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-------------
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total_msg_count_Request_Control: 2568 20544
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total_msg_count_Response_Data: 2562 184464
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total_msg_count_Writeback_Data: 2281 164232
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total_msg_count_Writeback_Control: 5351 42808
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total_msg_count_Unblock_Control: 2559 20472
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total_msgs: 15321 total_bytes: 432520
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 0.13593
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links_utilized_percent_switch_0_link_0: 0.0498829 bw: 640000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.221977 bw: 160000 base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Data: 761 54792 [ 0 0 0 0 0 761 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Control: 936 7488 [ 0 0 849 0 0 87 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 0.127495
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links_utilized_percent_switch_1_link_0: 0.0554358 bw: 640000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.199555 bw: 160000 base_latency: 1
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outgoing_messages_switch_1_link_0_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 849 6792 [ 0 0 0 849 0 0 0 0 0 0 ] base_latency: 1
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 0.210637
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links_utilized_percent_switch_2_link_0: 0.199531 bw: 160000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 0.221743 bw: 160000 base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
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Cache Stats: system.l1_cntrl0.sequencer.icache
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system.l1_cntrl0.sequencer.icache_total_misses: 57
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system.l1_cntrl0.sequencer.icache_total_demand_misses: 57
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system.l1_cntrl0.sequencer.icache_total_prefetches: 0
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system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
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system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
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system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
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system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 57 100%
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Cache Stats: system.l1_cntrl0.sequencer.dcache
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system.l1_cntrl0.sequencer.dcache_total_misses: 840
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system.l1_cntrl0.sequencer.dcache_total_demand_misses: 840
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system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
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system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
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system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
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system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.28571%
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system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.7143%
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system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 840 100%
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Cache Stats: system.l1_cntrl0.L2cacheMemory
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system.l1_cntrl0.L2cacheMemory_total_misses: 856
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system.l1_cntrl0.L2cacheMemory_total_demand_misses: 856
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system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
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system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
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system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
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system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.20561%
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system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.486%
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system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.30841%
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system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 856 100%
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--- L1Cache ---
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- Event Counts -
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Load [41 ] 41
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Ifetch [106 ] 106
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Store [906 ] 906
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L2_Replacement [849 ] 849
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L1_to_L2 [303164 ] 303164
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Trigger_L2_to_L1D [38 ] 38
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Trigger_L2_to_L1I [3 ] 3
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Complete_L2_to_L1 [41 ] 41
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Other_GETX [0 ] 0
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Other_GETS [0 ] 0
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Merged_GETS [0 ] 0
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|
Other_GETS_No_Mig [0 ] 0
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|
Invalidate [0 ] 0
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Ack [0 ] 0
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Shared_Ack [0 ] 0
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Data [0 ] 0
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Shared_Data [0 ] 0
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Exclusive_Data [854 ] 854
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Writeback_Ack [848 ] 848
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Writeback_Nack [0 ] 0
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All_acks [0 ] 0
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All_acks_no_sharers [853 ] 853
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- Transitions -
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I Load [36 ] 36
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I Ifetch [54 ] 54
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I Store [766 ] 766
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I L2_Replacement [0 ] 0
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I L1_to_L2 [0 ] 0
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I Trigger_L2_to_L1D [0 ] 0
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I Trigger_L2_to_L1I [0 ] 0
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I Other_GETX [0 ] 0
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I Other_GETS [0 ] 0
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I Other_GETS_No_Mig [0 ] 0
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I Invalidate [0 ] 0
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S Load [0 ] 0
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S Ifetch [0 ] 0
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S Store [0 ] 0
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S L2_Replacement [0 ] 0
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S L1_to_L2 [0 ] 0
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S Trigger_L2_to_L1D [0 ] 0
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S Trigger_L2_to_L1I [0 ] 0
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S Other_GETX [0 ] 0
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S Other_GETS [0 ] 0
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S Other_GETS_No_Mig [0 ] 0
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S Invalidate [0 ] 0
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O Load [0 ] 0
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O Ifetch [0 ] 0
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O Store [0 ] 0
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O L2_Replacement [0 ] 0
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O L1_to_L2 [0 ] 0
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O Trigger_L2_to_L1D [0 ] 0
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O Trigger_L2_to_L1I [0 ] 0
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O Other_GETX [0 ] 0
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O Other_GETS [0 ] 0
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O Merged_GETS [0 ] 0
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O Other_GETS_No_Mig [0 ] 0
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O Invalidate [0 ] 0
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M Load [0 ] 0
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M Ifetch [1 ] 1
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M Store [1 ] 1
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M L2_Replacement [87 ] 87
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M L1_to_L2 [88 ] 88
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M Trigger_L2_to_L1D [1 ] 1
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M Trigger_L2_to_L1I [0 ] 0
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M Other_GETX [0 ] 0
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M Other_GETS [0 ] 0
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M Merged_GETS [0 ] 0
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M Other_GETS_No_Mig [0 ] 0
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M Invalidate [0 ] 0
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MM Load [5 ] 5
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MM Ifetch [4 ] 4
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MM Store [82 ] 82
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MM L2_Replacement [762 ] 762
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MM L1_to_L2 [804 ] 804
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MM Trigger_L2_to_L1D [37 ] 37
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MM Trigger_L2_to_L1I [3 ] 3
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MM Other_GETX [0 ] 0
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MM Other_GETS [0 ] 0
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MM Merged_GETS [0 ] 0
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MM Other_GETS_No_Mig [0 ] 0
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MM Invalidate [0 ] 0
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IM Load [0 ] 0
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IM Ifetch [0 ] 0
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IM Store [0 ] 0
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IM L2_Replacement [0 ] 0
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IM L1_to_L2 [275518 ] 275518
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IM Other_GETX [0 ] 0
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IM Other_GETS [0 ] 0
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IM Other_GETS_No_Mig [0 ] 0
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IM Invalidate [0 ] 0
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IM Ack [0 ] 0
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IM Data [0 ] 0
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IM Exclusive_Data [764 ] 764
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SM Load [0 ] 0
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SM Ifetch [0 ] 0
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SM Store [0 ] 0
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SM L2_Replacement [0 ] 0
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SM L1_to_L2 [0 ] 0
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SM Other_GETX [0 ] 0
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SM Other_GETS [0 ] 0
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SM Other_GETS_No_Mig [0 ] 0
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SM Invalidate [0 ] 0
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SM Ack [0 ] 0
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SM Data [0 ] 0
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OM Load [0 ] 0
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OM Ifetch [0 ] 0
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OM Store [0 ] 0
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OM L2_Replacement [0 ] 0
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OM L1_to_L2 [0 ] 0
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OM Other_GETX [0 ] 0
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OM Other_GETS [0 ] 0
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OM Merged_GETS [0 ] 0
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OM Other_GETS_No_Mig [0 ] 0
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OM Invalidate [0 ] 0
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OM Ack [0 ] 0
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OM All_acks [0 ] 0
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OM All_acks_no_sharers [0 ] 0
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ISM Load [0 ] 0
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ISM Ifetch [0 ] 0
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ISM Store [0 ] 0
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ISM L2_Replacement [0 ] 0
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ISM L1_to_L2 [0 ] 0
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ISM Ack [0 ] 0
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ISM All_acks_no_sharers [0 ] 0
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M_W Load [0 ] 0
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M_W Ifetch [0 ] 0
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M_W Store [0 ] 0
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M_W L2_Replacement [0 ] 0
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M_W L1_to_L2 [483 ] 483
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M_W Ack [0 ] 0
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M_W All_acks_no_sharers [89 ] 89
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MM_W Load [0 ] 0
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MM_W Ifetch [0 ] 0
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MM_W Store [1 ] 1
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MM_W L2_Replacement [0 ] 0
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MM_W L1_to_L2 [10887 ] 10887
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MM_W Ack [0 ] 0
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MM_W All_acks_no_sharers [764 ] 764
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IS Load [0 ] 0
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IS Ifetch [0 ] 0
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IS Store [0 ] 0
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IS L2_Replacement [0 ] 0
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IS L1_to_L2 [14644 ] 14644
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IS Other_GETX [0 ] 0
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IS Other_GETS [0 ] 0
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IS Other_GETS_No_Mig [0 ] 0
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IS Invalidate [0 ] 0
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IS Ack [0 ] 0
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IS Shared_Ack [0 ] 0
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IS Data [0 ] 0
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IS Shared_Data [0 ] 0
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IS Exclusive_Data [90 ] 90
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SS Load [0 ] 0
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SS Ifetch [0 ] 0
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SS Store [0 ] 0
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SS L2_Replacement [0 ] 0
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SS L1_to_L2 [0 ] 0
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SS Ack [0 ] 0
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SS Shared_Ack [0 ] 0
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SS All_acks [0 ] 0
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SS All_acks_no_sharers [0 ] 0
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OI Load [0 ] 0
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OI Ifetch [0 ] 0
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OI Store [0 ] 0
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OI L2_Replacement [0 ] 0
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OI L1_to_L2 [0 ] 0
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OI Other_GETX [0 ] 0
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OI Other_GETS [0 ] 0
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OI Merged_GETS [0 ] 0
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OI Other_GETS_No_Mig [0 ] 0
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OI Invalidate [0 ] 0
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OI Writeback_Ack [0 ] 0
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MI Load [0 ] 0
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MI Ifetch [36 ] 36
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MI Store [5 ] 5
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MI L2_Replacement [0 ] 0
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MI L1_to_L2 [0 ] 0
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MI Other_GETX [0 ] 0
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MI Other_GETS [0 ] 0
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MI Merged_GETS [0 ] 0
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MI Other_GETS_No_Mig [0 ] 0
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MI Invalidate [0 ] 0
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MI Writeback_Ack [848 ] 848
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II Load [0 ] 0
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II Ifetch [0 ] 0
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II Store [0 ] 0
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II L2_Replacement [0 ] 0
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II L1_to_L2 [0 ] 0
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II Other_GETX [0 ] 0
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II Other_GETS [0 ] 0
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II Other_GETS_No_Mig [0 ] 0
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II Invalidate [0 ] 0
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II Writeback_Ack [0 ] 0
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II Writeback_Nack [0 ] 0
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IT Load [0 ] 0
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IT Ifetch [0 ] 0
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IT Store [0 ] 0
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IT L2_Replacement [0 ] 0
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IT L1_to_L2 [0 ] 0
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IT Complete_L2_to_L1 [0 ] 0
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IT Other_GETX [0 ] 0
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IT Other_GETS [0 ] 0
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IT Merged_GETS [0 ] 0
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IT Other_GETS_No_Mig [0 ] 0
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IT Invalidate [0 ] 0
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ST Load [0 ] 0
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ST Ifetch [0 ] 0
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ST Store [0 ] 0
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ST L2_Replacement [0 ] 0
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ST L1_to_L2 [0 ] 0
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ST Complete_L2_to_L1 [0 ] 0
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ST Other_GETX [0 ] 0
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ST Other_GETS [0 ] 0
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ST Merged_GETS [0 ] 0
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ST Other_GETS_No_Mig [0 ] 0
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ST Invalidate [0 ] 0
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OT Load [0 ] 0
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OT Ifetch [0 ] 0
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OT Store [0 ] 0
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OT L2_Replacement [0 ] 0
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OT L1_to_L2 [0 ] 0
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OT Complete_L2_to_L1 [0 ] 0
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OT Other_GETX [0 ] 0
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OT Other_GETS [0 ] 0
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OT Merged_GETS [0 ] 0
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OT Other_GETS_No_Mig [0 ] 0
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OT Invalidate [0 ] 0
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MT Load [0 ] 0
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MT Ifetch [0 ] 0
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MT Store [10 ] 10
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MT L2_Replacement [0 ] 0
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MT L1_to_L2 [154 ] 154
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MT Complete_L2_to_L1 [1 ] 1
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MT Other_GETX [0 ] 0
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MT Other_GETS [0 ] 0
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MT Merged_GETS [0 ] 0
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MT Other_GETS_No_Mig [0 ] 0
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MT Invalidate [0 ] 0
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MMT Load [0 ] 0
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MMT Ifetch [11 ] 11
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MMT Store [41 ] 41
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MMT L2_Replacement [0 ] 0
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MMT L1_to_L2 [586 ] 586
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MMT Complete_L2_to_L1 [40 ] 40
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MMT Other_GETX [0 ] 0
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MMT Other_GETS [0 ] 0
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MMT Merged_GETS [0 ] 0
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MMT Other_GETS_No_Mig [0 ] 0
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MMT Invalidate [0 ] 0
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Cache Stats: system.dir_cntrl0.probeFilter
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system.dir_cntrl0.probeFilter_total_misses: 0
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system.dir_cntrl0.probeFilter_total_demand_misses: 0
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system.dir_cntrl0.probeFilter_total_prefetches: 0
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system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
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system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
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Memory controller: system.dir_cntrl0.memBuffer:
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memory_total_requests: 1616
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memory_reads: 856
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memory_writes: 760
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memory_refreshes: 446
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memory_total_request_delays: 1108
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memory_delays_per_request: 0.685644
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memory_delays_in_input_queue: 161
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memory_delays_behind_head_of_bank_queue: 2
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memory_delays_stalled_at_head_of_bank_queue: 945
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memory_stalls_for_bank_busy: 192
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memory_stalls_for_random_busy: 0
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memory_stalls_for_anti_starvation: 0
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memory_stalls_for_arbitration: 83
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memory_stalls_for_bus: 395
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memory_stalls_for_tfaw: 0
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memory_stalls_for_read_write_turnaround: 154
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memory_stalls_for_read_read_turnaround: 121
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accesses_per_bank: 34 44 48 84 67 62 61 53 41 30 54 49 46 47 41 52 49 35 67 45 67 44 44 46 55 52 53 50 44 47 56 49
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--- Directory ---
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- Event Counts -
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GETX [770 ] 770
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GETS [91 ] 91
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PUT [909 ] 909
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Unblock [0 ] 0
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UnblockS [0 ] 0
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UnblockM [853 ] 853
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Writeback_Clean [0 ] 0
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Writeback_Dirty [0 ] 0
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Writeback_Exclusive_Clean [86 ] 86
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Writeback_Exclusive_Dirty [760 ] 760
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Pf_Replacement [0 ] 0
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DMA_READ [0 ] 0
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DMA_WRITE [0 ] 0
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Memory_Data [854 ] 854
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Memory_Ack [760 ] 760
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Ack [0 ] 0
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Shared_Ack [0 ] 0
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Shared_Data [0 ] 0
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Data [0 ] 0
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Exclusive_Data [0 ] 0
|
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All_acks_and_shared_data [0 ] 0
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All_acks_and_owner_data [0 ] 0
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All_acks_and_data_no_sharers [0 ] 0
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All_Unblocks [0 ] 0
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- Transitions -
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NX GETX [0 ] 0
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NX GETS [0 ] 0
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NX PUT [0 ] 0
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NX Pf_Replacement [0 ] 0
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NX DMA_READ [0 ] 0
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NX DMA_WRITE [0 ] 0
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NO GETX [0 ] 0
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NO GETS [0 ] 0
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NO PUT [849 ] 849
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NO Pf_Replacement [0 ] 0
|
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NO DMA_READ [0 ] 0
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NO DMA_WRITE [0 ] 0
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S GETX [0 ] 0
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S GETS [0 ] 0
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S PUT [0 ] 0
|
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S Pf_Replacement [0 ] 0
|
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S DMA_READ [0 ] 0
|
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S DMA_WRITE [0 ] 0
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O GETX [0 ] 0
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O GETS [0 ] 0
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O PUT [0 ] 0
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O Pf_Replacement [0 ] 0
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O DMA_READ [0 ] 0
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O DMA_WRITE [0 ] 0
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E GETX [766 ] 766
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E GETS [90 ] 90
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E PUT [0 ] 0
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E DMA_READ [0 ] 0
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E DMA_WRITE [0 ] 0
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O_R GETX [0 ] 0
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O_R GETS [0 ] 0
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O_R PUT [0 ] 0
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O_R Pf_Replacement [0 ] 0
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O_R DMA_READ [0 ] 0
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O_R DMA_WRITE [0 ] 0
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O_R Ack [0 ] 0
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O_R All_acks_and_data_no_sharers [0 ] 0
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S_R GETX [0 ] 0
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S_R GETS [0 ] 0
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S_R PUT [0 ] 0
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S_R Pf_Replacement [0 ] 0
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S_R DMA_READ [0 ] 0
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S_R DMA_WRITE [0 ] 0
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S_R Ack [0 ] 0
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S_R Data [0 ] 0
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S_R All_acks_and_data_no_sharers [0 ] 0
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NO_R GETX [0 ] 0
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NO_R GETS [0 ] 0
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NO_R PUT [0 ] 0
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NO_R Pf_Replacement [0 ] 0
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NO_R DMA_READ [0 ] 0
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NO_R DMA_WRITE [0 ] 0
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NO_R Ack [0 ] 0
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NO_R Data [0 ] 0
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NO_R Exclusive_Data [0 ] 0
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NO_R All_acks_and_data_no_sharers [0 ] 0
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NO_B GETX [0 ] 0
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NO_B GETS [0 ] 0
|
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NO_B PUT [60 ] 60
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|
NO_B UnblockS [0 ] 0
|
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NO_B UnblockM [853 ] 853
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|
NO_B Pf_Replacement [0 ] 0
|
|
NO_B DMA_READ [0 ] 0
|
|
NO_B DMA_WRITE [0 ] 0
|
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NO_B_X GETX [0 ] 0
|
|
NO_B_X GETS [0 ] 0
|
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NO_B_X PUT [0 ] 0
|
|
NO_B_X UnblockS [0 ] 0
|
|
NO_B_X UnblockM [0 ] 0
|
|
NO_B_X Pf_Replacement [0 ] 0
|
|
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NO_B_S GETX [0 ] 0
|
|
NO_B_S GETS [0 ] 0
|
|
NO_B_S PUT [0 ] 0
|
|
NO_B_S UnblockS [0 ] 0
|
|
NO_B_S UnblockM [0 ] 0
|
|
NO_B_S Pf_Replacement [0 ] 0
|
|
NO_B_S DMA_READ [0 ] 0
|
|
NO_B_S DMA_WRITE [0 ] 0
|
|
|
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NO_B_S_W GETX [0 ] 0
|
|
NO_B_S_W GETS [0 ] 0
|
|
NO_B_S_W PUT [0 ] 0
|
|
NO_B_S_W UnblockS [0 ] 0
|
|
NO_B_S_W Pf_Replacement [0 ] 0
|
|
NO_B_S_W DMA_READ [0 ] 0
|
|
NO_B_S_W DMA_WRITE [0 ] 0
|
|
NO_B_S_W All_Unblocks [0 ] 0
|
|
|
|
O_B GETX [0 ] 0
|
|
O_B GETS [0 ] 0
|
|
O_B PUT [0 ] 0
|
|
O_B UnblockS [0 ] 0
|
|
O_B Pf_Replacement [0 ] 0
|
|
O_B DMA_READ [0 ] 0
|
|
O_B DMA_WRITE [0 ] 0
|
|
|
|
NO_B_W GETX [0 ] 0
|
|
NO_B_W GETS [0 ] 0
|
|
NO_B_W PUT [0 ] 0
|
|
NO_B_W UnblockS [0 ] 0
|
|
NO_B_W UnblockM [0 ] 0
|
|
NO_B_W Pf_Replacement [0 ] 0
|
|
NO_B_W DMA_READ [0 ] 0
|
|
NO_B_W DMA_WRITE [0 ] 0
|
|
NO_B_W Memory_Data [854 ] 854
|
|
|
|
O_B_W GETX [0 ] 0
|
|
O_B_W GETS [0 ] 0
|
|
O_B_W PUT [0 ] 0
|
|
O_B_W UnblockS [0 ] 0
|
|
O_B_W Pf_Replacement [0 ] 0
|
|
O_B_W DMA_READ [0 ] 0
|
|
O_B_W DMA_WRITE [0 ] 0
|
|
O_B_W Memory_Data [0 ] 0
|
|
|
|
NO_W GETX [0 ] 0
|
|
NO_W GETS [0 ] 0
|
|
NO_W PUT [0 ] 0
|
|
NO_W Pf_Replacement [0 ] 0
|
|
NO_W DMA_READ [0 ] 0
|
|
NO_W DMA_WRITE [0 ] 0
|
|
NO_W Memory_Data [0 ] 0
|
|
|
|
O_W GETX [0 ] 0
|
|
O_W GETS [0 ] 0
|
|
O_W PUT [0 ] 0
|
|
O_W Pf_Replacement [0 ] 0
|
|
O_W DMA_READ [0 ] 0
|
|
O_W DMA_WRITE [0 ] 0
|
|
O_W Memory_Data [0 ] 0
|
|
|
|
NO_DW_B_W GETX [0 ] 0
|
|
NO_DW_B_W GETS [0 ] 0
|
|
NO_DW_B_W PUT [0 ] 0
|
|
NO_DW_B_W Pf_Replacement [0 ] 0
|
|
NO_DW_B_W DMA_READ [0 ] 0
|
|
NO_DW_B_W DMA_WRITE [0 ] 0
|
|
NO_DW_B_W Ack [0 ] 0
|
|
NO_DW_B_W Data [0 ] 0
|
|
NO_DW_B_W Exclusive_Data [0 ] 0
|
|
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
|
|
|
NO_DR_B_W GETX [0 ] 0
|
|
NO_DR_B_W GETS [0 ] 0
|
|
NO_DR_B_W PUT [0 ] 0
|
|
NO_DR_B_W Pf_Replacement [0 ] 0
|
|
NO_DR_B_W DMA_READ [0 ] 0
|
|
NO_DR_B_W DMA_WRITE [0 ] 0
|
|
NO_DR_B_W Memory_Data [0 ] 0
|
|
NO_DR_B_W Ack [0 ] 0
|
|
NO_DR_B_W Shared_Ack [0 ] 0
|
|
NO_DR_B_W Shared_Data [0 ] 0
|
|
NO_DR_B_W Data [0 ] 0
|
|
NO_DR_B_W Exclusive_Data [0 ] 0
|
|
|
|
NO_DR_B_D GETX [0 ] 0
|
|
NO_DR_B_D GETS [0 ] 0
|
|
NO_DR_B_D PUT [0 ] 0
|
|
NO_DR_B_D Pf_Replacement [0 ] 0
|
|
NO_DR_B_D DMA_READ [0 ] 0
|
|
NO_DR_B_D DMA_WRITE [0 ] 0
|
|
NO_DR_B_D Ack [0 ] 0
|
|
NO_DR_B_D Shared_Ack [0 ] 0
|
|
NO_DR_B_D Shared_Data [0 ] 0
|
|
NO_DR_B_D Data [0 ] 0
|
|
NO_DR_B_D Exclusive_Data [0 ] 0
|
|
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
|
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
|
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
|
|
|
NO_DR_B GETX [0 ] 0
|
|
NO_DR_B GETS [0 ] 0
|
|
NO_DR_B PUT [0 ] 0
|
|
NO_DR_B Pf_Replacement [0 ] 0
|
|
NO_DR_B DMA_READ [0 ] 0
|
|
NO_DR_B DMA_WRITE [0 ] 0
|
|
NO_DR_B Ack [0 ] 0
|
|
NO_DR_B Shared_Ack [0 ] 0
|
|
NO_DR_B Shared_Data [0 ] 0
|
|
NO_DR_B Data [0 ] 0
|
|
NO_DR_B Exclusive_Data [0 ] 0
|
|
NO_DR_B All_acks_and_shared_data [0 ] 0
|
|
NO_DR_B All_acks_and_owner_data [0 ] 0
|
|
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
|
|
|
NO_DW_W GETX [0 ] 0
|
|
NO_DW_W GETS [0 ] 0
|
|
NO_DW_W PUT [0 ] 0
|
|
NO_DW_W Pf_Replacement [0 ] 0
|
|
NO_DW_W DMA_READ [0 ] 0
|
|
NO_DW_W DMA_WRITE [0 ] 0
|
|
NO_DW_W Memory_Ack [0 ] 0
|
|
|
|
O_DR_B_W GETX [0 ] 0
|
|
O_DR_B_W GETS [0 ] 0
|
|
O_DR_B_W PUT [0 ] 0
|
|
O_DR_B_W Pf_Replacement [0 ] 0
|
|
O_DR_B_W DMA_READ [0 ] 0
|
|
O_DR_B_W DMA_WRITE [0 ] 0
|
|
O_DR_B_W Memory_Data [0 ] 0
|
|
O_DR_B_W Ack [0 ] 0
|
|
O_DR_B_W Shared_Ack [0 ] 0
|
|
|
|
O_DR_B GETX [0 ] 0
|
|
O_DR_B GETS [0 ] 0
|
|
O_DR_B PUT [0 ] 0
|
|
O_DR_B Pf_Replacement [0 ] 0
|
|
O_DR_B DMA_READ [0 ] 0
|
|
O_DR_B DMA_WRITE [0 ] 0
|
|
O_DR_B Ack [0 ] 0
|
|
O_DR_B Shared_Ack [0 ] 0
|
|
O_DR_B All_acks_and_owner_data [0 ] 0
|
|
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
|
|
|
WB GETX [2 ] 2
|
|
WB GETS [1 ] 1
|
|
WB PUT [0 ] 0
|
|
WB Unblock [0 ] 0
|
|
WB Writeback_Clean [0 ] 0
|
|
WB Writeback_Dirty [0 ] 0
|
|
WB Writeback_Exclusive_Clean [86 ] 86
|
|
WB Writeback_Exclusive_Dirty [760 ] 760
|
|
WB Pf_Replacement [0 ] 0
|
|
WB DMA_READ [0 ] 0
|
|
WB DMA_WRITE [0 ] 0
|
|
|
|
WB_O_W GETX [0 ] 0
|
|
WB_O_W GETS [0 ] 0
|
|
WB_O_W PUT [0 ] 0
|
|
WB_O_W Pf_Replacement [0 ] 0
|
|
WB_O_W DMA_READ [0 ] 0
|
|
WB_O_W DMA_WRITE [0 ] 0
|
|
WB_O_W Memory_Ack [0 ] 0
|
|
|
|
WB_E_W GETX [2 ] 2
|
|
WB_E_W GETS [0 ] 0
|
|
WB_E_W PUT [0 ] 0
|
|
WB_E_W Pf_Replacement [0 ] 0
|
|
WB_E_W DMA_READ [0 ] 0
|
|
WB_E_W DMA_WRITE [0 ] 0
|
|
WB_E_W Memory_Ack |