1d3228481f
On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0).
79 lines
3.9 KiB
Python
79 lines
3.9 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5.proxy import Self
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from MemObject import MemObject
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class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
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class BaseCache(MemObject):
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type = 'BaseCache'
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assoc = Param.Int("associativity")
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block_size = Param.Int("block size in bytes")
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latency = Param.Latency("Latency")
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hash_delay = Param.Int(1, "time in cycles of hash access")
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max_miss_count = Param.Counter(0,
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"number of misses to handle before calling exit")
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mshrs = Param.Int("number of MSHRs (max outstanding requests)")
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prioritizeRequests = Param.Bool(False,
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"always service demand misses first")
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repl = Param.Repl(NULL, "replacement policy")
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num_cpus = Param.Int(1, "number of cpus sharing this cache")
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size = Param.MemorySize("capacity in bytes")
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forward_snoops = Param.Bool(True,
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"forward snoops from mem side to cpu side")
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subblock_size = Param.Int(0,
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"Size of subblock in IIC used for compression")
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tgts_per_mshr = Param.Int("max number of accesses per MSHR")
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trace_addr = Param.Addr(0, "address to trace")
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two_queue = Param.Bool(False,
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"whether the lifo should have two queue replacement")
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write_buffers = Param.Int(8, "number of write buffers")
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prefetch_on_access = Param.Bool(False,
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"notify the hardware prefetcher on every access (not just misses)")
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prefetcher_size = Param.Int(100,
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"Number of entries in the hardware prefetch queue")
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prefetch_past_page = Param.Bool(False,
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"Allow prefetches to cross virtual page boundaries")
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prefetch_serial_squash = Param.Bool(False,
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"Squash prefetches with a later time on a subsequent miss")
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prefetch_degree = Param.Int(1,
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"Degree of the prefetch depth")
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prefetch_latency = Param.Latency(10 * Self.latency,
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"Latency of the prefetcher")
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prefetch_policy = Param.Prefetch('none',
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"Type of prefetcher to use")
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prefetch_use_cpu_id = Param.Bool(True,
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"Use the CPU ID to separate calculations of prefetches")
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prefetch_data_accesses_only = Param.Bool(False,
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"Only prefetch on data not on instruction accesses")
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cpu_side = Port("Port on side closer to CPU")
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mem_side = Port("Port on side closer to MEM")
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addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
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