20e9a90edc
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
33 lines
1.1 KiB
Text
33 lines
1.1 KiB
Text
def operand_types {{
|
|
'sb' : ('signed int', 8),
|
|
'ub' : ('unsigned int', 8),
|
|
'sh' : ('signed int', 16),
|
|
'uh' : ('unsigned int', 16),
|
|
'sw' : ('signed int', 32),
|
|
'uw' : ('unsigned int', 32),
|
|
'sd' : ('signed int', 64),
|
|
'ud' : ('unsigned int', 64),
|
|
'sf' : ('float', 32),
|
|
'df' : ('float', 64),
|
|
'qf' : ('float', 128)
|
|
}};
|
|
|
|
def operands {{
|
|
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
|
|
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
|
|
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
|
|
'r31': ('IntReg', 'uw','R31','IsInteger', 4),
|
|
'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
|
|
|
|
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
|
|
|
|
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
|
|
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
|
|
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
|
|
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
|
|
|
|
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
|
|
|
'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
|
|
'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
|
|
}};
|