Andreas Hansson e65de3f5ca config: Do not use hardcoded physmem in fs script ... This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system.		2013-01-07 13:05:38 -05:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	Regression: Use CPU clock and 32-byte width for L1-L2 bus	2012-10-15 08:08:08 -04:00
Caches.py	config: Unify caches used in regressions and adjust L2 MSHRs	2012-10-30 07:44:08 -04:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	config: Do not use hardcoded physmem in fs script	2013-01-07 13:05:38 -05:00
O3_ARM_v7a.py	TournamentBP: Fix some bugs with table sizes and counters	2012-12-06 09:31:06 -06:00
Options.py	config: Fix description of checkpoint option from cycle to tick	2012-11-19 11:21:09 -05:00
Simulation.py	python: Rename doDrain()->drain() and make it do the right thing	2012-11-02 11:32:02 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00