173a786921
This patch allows the ruby random tester to use ruby ports that may only support instr or data requests. This patch is similar to a previous changeset (8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets. This current patch implements the support in a more straight-forward way. Since retries are now tested when running the ruby random tester, this patch splits up the retry and drain check behavior so that RubyPort children, such as the GPUCoalescer, can perform those operations correctly without having to duplicate code. Finally, the patch also includes better DPRINTFs for debugging the tester.
86 lines
3.7 KiB
Python
86 lines
3.7 KiB
Python
# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Brad Beckmann
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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class RubyPort(MemObject):
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type = 'RubyPort'
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abstract = True
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cxx_header = "mem/ruby/system/RubyPort.hh"
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version = Param.Int(0, "")
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slave = VectorSlavePort("CPU slave port")
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master = VectorMasterPort("CPU master port")
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pio_master_port = MasterPort("Ruby mem master port")
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mem_master_port = MasterPort("Ruby mem master port")
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pio_slave_port = SlavePort("Ruby pio slave port")
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mem_slave_port = SlavePort("Ruby memory port")
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using_ruby_tester = Param.Bool(False, "")
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no_retry_on_stall = Param.Bool(False, "")
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ruby_system = Param.RubySystem(Parent.any, "")
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system = Param.System(Parent.any, "system object")
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support_data_reqs = Param.Bool(True, "data cache requests supported")
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support_inst_reqs = Param.Bool(True, "inst cache requests supported")
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class RubyPortProxy(RubyPort):
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type = 'RubyPortProxy'
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cxx_header = "mem/ruby/system/RubyPortProxy.hh"
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class RubySequencer(RubyPort):
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type = 'RubySequencer'
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cxx_class = 'Sequencer'
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cxx_header = "mem/ruby/system/Sequencer.hh"
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icache = Param.RubyCache("")
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dcache = Param.RubyCache("")
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# Cache latencies currently assessed at the beginning of each access
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# NOTE: Setting these values to a value greater than one will result in
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# O3 CPU pipeline bubbles and negatively impact performance
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# TODO: Latencies should be migrated into each top-level cache controller
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icache_hit_latency = Param.Cycles(1, "Inst cache hit latency")
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dcache_hit_latency = Param.Cycles(1, "Data cache hit latency")
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max_outstanding_requests = Param.Int(16,
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"max requests (incl. prefetches) outstanding")
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deadlock_threshold = Param.Cycles(500000,
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"max outstanding cycles for a request before deadlock/livelock declared")
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using_network_tester = Param.Bool(False, "")
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class DMASequencer(MemObject):
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type = 'DMASequencer'
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cxx_header = "mem/ruby/system/DMASequencer.hh"
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version = Param.Int(0, "")
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slave = SlavePort("Device slave port")
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using_ruby_tester = Param.Bool(False, "")
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ruby_system = Param.RubySystem(Parent.any, "")
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system = Param.System(Parent.any, "system object")
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