173a786921
This patch allows the ruby random tester to use ruby ports that may only support instr or data requests. This patch is similar to a previous changeset (8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets. This current patch implements the support in a more straight-forward way. Since retries are now tested when running the ruby random tester, this patch splits up the retry and drain check behavior so that RubyPort children, such as the GPUCoalescer, can perform those operations correctly without having to duplicate code. Finally, the patch also includes better DPRINTFs for debugging the tester.
757 lines
27 KiB
C++
757 lines
27 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/x86/ldstflags.hh"
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#include "base/misc.hh"
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#include "base/str.hh"
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#include "cpu/testers/rubytest/RubyTester.hh"
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#include "debug/MemoryAccess.hh"
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#include "debug/ProtocolTrace.hh"
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#include "debug/RubySequencer.hh"
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#include "debug/RubyStats.hh"
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#include "mem/protocol/PrefetchBit.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/slicc_interface/RubyRequest.hh"
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#include "mem/ruby/system/RubySystem.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "mem/packet.hh"
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#include "sim/system.hh"
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using namespace std;
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Sequencer *
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RubySequencerParams::create()
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{
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return new Sequencer(this);
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}
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Sequencer::Sequencer(const Params *p)
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: RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this)
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{
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m_outstanding_count = 0;
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m_instCache_ptr = p->icache;
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m_dataCache_ptr = p->dcache;
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m_data_cache_hit_latency = p->dcache_hit_latency;
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m_inst_cache_hit_latency = p->icache_hit_latency;
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m_max_outstanding_requests = p->max_outstanding_requests;
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m_deadlock_threshold = p->deadlock_threshold;
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assert(m_max_outstanding_requests > 0);
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assert(m_deadlock_threshold > 0);
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assert(m_instCache_ptr != NULL);
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assert(m_dataCache_ptr != NULL);
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assert(m_data_cache_hit_latency > 0);
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assert(m_inst_cache_hit_latency > 0);
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m_usingNetworkTester = p->using_network_tester;
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}
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Sequencer::~Sequencer()
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{
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}
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void
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Sequencer::wakeup()
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{
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assert(drainState() != DrainState::Draining);
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// Check for deadlock of any of the requests
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Cycles current_time = curCycle();
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// Check across all outstanding requests
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int total_outstanding = 0;
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RequestTable::iterator read = m_readRequestTable.begin();
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RequestTable::iterator read_end = m_readRequestTable.end();
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for (; read != read_end; ++read) {
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SequencerRequest* request = read->second;
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if (current_time - request->issue_time < m_deadlock_threshold)
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continue;
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panic("Possible Deadlock detected. Aborting!\n"
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"version: %d request.paddr: 0x%x m_readRequestTable: %d "
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"current time: %u issue_time: %d difference: %d\n", m_version,
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request->pkt->getAddr(), m_readRequestTable.size(),
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current_time * clockPeriod(), request->issue_time * clockPeriod(),
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(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
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}
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RequestTable::iterator write = m_writeRequestTable.begin();
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RequestTable::iterator write_end = m_writeRequestTable.end();
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for (; write != write_end; ++write) {
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SequencerRequest* request = write->second;
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if (current_time - request->issue_time < m_deadlock_threshold)
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continue;
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panic("Possible Deadlock detected. Aborting!\n"
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"version: %d request.paddr: 0x%x m_writeRequestTable: %d "
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"current time: %u issue_time: %d difference: %d\n", m_version,
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request->pkt->getAddr(), m_writeRequestTable.size(),
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current_time * clockPeriod(), request->issue_time * clockPeriod(),
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(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
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}
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total_outstanding += m_writeRequestTable.size();
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total_outstanding += m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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if (m_outstanding_count > 0) {
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// If there are still outstanding requests, keep checking
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schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
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}
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}
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void Sequencer::resetStats()
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{
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m_latencyHist.reset();
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m_hitLatencyHist.reset();
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m_missLatencyHist.reset();
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for (int i = 0; i < RubyRequestType_NUM; i++) {
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m_typeLatencyHist[i]->reset();
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m_hitTypeLatencyHist[i]->reset();
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m_missTypeLatencyHist[i]->reset();
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for (int j = 0; j < MachineType_NUM; j++) {
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m_hitTypeMachLatencyHist[i][j]->reset();
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m_missTypeMachLatencyHist[i][j]->reset();
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}
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}
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for (int i = 0; i < MachineType_NUM; i++) {
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m_missMachLatencyHist[i]->reset();
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m_hitMachLatencyHist[i]->reset();
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m_IssueToInitialDelayHist[i]->reset();
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m_InitialToForwardDelayHist[i]->reset();
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m_ForwardToFirstResponseDelayHist[i]->reset();
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m_FirstResponseToCompletionDelayHist[i]->reset();
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m_IncompleteTimes[i] = 0;
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}
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}
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// Insert the request on the correct request table. Return true if
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// the entry was already present.
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RequestStatus
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Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
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{
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assert(m_outstanding_count ==
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(m_writeRequestTable.size() + m_readRequestTable.size()));
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// See if we should schedule a deadlock check
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if (!deadlockCheckEvent.scheduled() &&
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drainState() != DrainState::Draining) {
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schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
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}
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Addr line_addr = makeLineAddress(pkt->getAddr());
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// Create a default entry, mapping the address to NULL, the cast is
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// there to make gcc 4.4 happy
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RequestTable::value_type default_entry(line_addr,
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(SequencerRequest*) NULL);
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if ((request_type == RubyRequestType_ST) ||
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(request_type == RubyRequestType_RMW_Read) ||
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(request_type == RubyRequestType_RMW_Write) ||
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(request_type == RubyRequestType_Load_Linked) ||
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(request_type == RubyRequestType_Store_Conditional) ||
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(request_type == RubyRequestType_Locked_RMW_Read) ||
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(request_type == RubyRequestType_Locked_RMW_Write) ||
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(request_type == RubyRequestType_FLUSH)) {
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// Check if there is any outstanding read request for the same
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// cache line.
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if (m_readRequestTable.count(line_addr) > 0) {
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m_store_waiting_on_load++;
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return RequestStatus_Aliased;
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}
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pair<RequestTable::iterator, bool> r =
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m_writeRequestTable.insert(default_entry);
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if (r.second) {
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RequestTable::iterator i = r.first;
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i->second = new SequencerRequest(pkt, request_type, curCycle());
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m_outstanding_count++;
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} else {
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// There is an outstanding write request for the cache line
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m_store_waiting_on_store++;
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return RequestStatus_Aliased;
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}
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} else {
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// Check if there is any outstanding write request for the same
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// cache line.
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if (m_writeRequestTable.count(line_addr) > 0) {
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m_load_waiting_on_store++;
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return RequestStatus_Aliased;
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}
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pair<RequestTable::iterator, bool> r =
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m_readRequestTable.insert(default_entry);
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if (r.second) {
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RequestTable::iterator i = r.first;
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i->second = new SequencerRequest(pkt, request_type, curCycle());
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m_outstanding_count++;
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} else {
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// There is an outstanding read request for the cache line
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m_load_waiting_on_load++;
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return RequestStatus_Aliased;
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}
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}
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m_outstandReqHist.sample(m_outstanding_count);
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assert(m_outstanding_count ==
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(m_writeRequestTable.size() + m_readRequestTable.size()));
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return RequestStatus_Ready;
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}
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void
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Sequencer::markRemoved()
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{
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m_outstanding_count--;
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assert(m_outstanding_count ==
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m_writeRequestTable.size() + m_readRequestTable.size());
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}
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void
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Sequencer::invalidateSC(Addr address)
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{
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AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
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// The controller has lost the coherence permissions, hence the lock
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// on the cache line maintained by the cache should be cleared.
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if (e && e->isLocked(m_version)) {
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e->clearLocked();
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}
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}
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bool
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Sequencer::handleLlsc(Addr address, SequencerRequest* request)
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{
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AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
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if (!e)
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return true;
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// The success flag indicates whether the LLSC operation was successful.
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// LL ops will always succeed, but SC may fail if the cache line is no
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// longer locked.
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bool success = true;
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if (request->m_type == RubyRequestType_Store_Conditional) {
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if (!e->isLocked(m_version)) {
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//
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// For failed SC requests, indicate the failure to the cpu by
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// setting the extra data to zero.
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//
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request->pkt->req->setExtraData(0);
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success = false;
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} else {
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//
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// For successful SC requests, indicate the success to the cpu by
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// setting the extra data to one.
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//
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request->pkt->req->setExtraData(1);
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}
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//
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// Independent of success, all SC operations must clear the lock
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//
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e->clearLocked();
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} else if (request->m_type == RubyRequestType_Load_Linked) {
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//
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// Note: To fully follow Alpha LLSC semantics, should the LL clear any
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// previously locked cache lines?
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//
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e->setLocked(m_version);
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} else if (e->isLocked(m_version)) {
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//
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// Normal writes should clear the locked address
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//
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e->clearLocked();
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}
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return success;
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}
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void
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Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
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const MachineType respondingMach,
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bool isExternalHit, Cycles issuedTime,
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Cycles initialRequestTime,
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Cycles forwardRequestTime,
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Cycles firstResponseTime, Cycles completionTime)
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{
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m_latencyHist.sample(cycles);
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m_typeLatencyHist[type]->sample(cycles);
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if (isExternalHit) {
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m_missLatencyHist.sample(cycles);
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m_missTypeLatencyHist[type]->sample(cycles);
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if (respondingMach != MachineType_NUM) {
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m_missMachLatencyHist[respondingMach]->sample(cycles);
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m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles);
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if ((issuedTime <= initialRequestTime) &&
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(initialRequestTime <= forwardRequestTime) &&
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(forwardRequestTime <= firstResponseTime) &&
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(firstResponseTime <= completionTime)) {
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m_IssueToInitialDelayHist[respondingMach]->sample(
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initialRequestTime - issuedTime);
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m_InitialToForwardDelayHist[respondingMach]->sample(
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forwardRequestTime - initialRequestTime);
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m_ForwardToFirstResponseDelayHist[respondingMach]->sample(
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firstResponseTime - forwardRequestTime);
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m_FirstResponseToCompletionDelayHist[respondingMach]->sample(
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completionTime - firstResponseTime);
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} else {
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m_IncompleteTimes[respondingMach]++;
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}
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}
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} else {
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m_hitLatencyHist.sample(cycles);
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m_hitTypeLatencyHist[type]->sample(cycles);
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if (respondingMach != MachineType_NUM) {
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m_hitMachLatencyHist[respondingMach]->sample(cycles);
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m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles);
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}
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}
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}
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void
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Sequencer::writeCallback(Addr address, DataBlock& data,
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const bool externalHit, const MachineType mach,
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const Cycles initialRequestTime,
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const Cycles forwardRequestTime,
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const Cycles firstResponseTime)
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{
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assert(address == makeLineAddress(address));
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assert(m_writeRequestTable.count(makeLineAddress(address)));
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RequestTable::iterator i = m_writeRequestTable.find(address);
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assert(i != m_writeRequestTable.end());
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SequencerRequest* request = i->second;
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m_writeRequestTable.erase(i);
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markRemoved();
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assert((request->m_type == RubyRequestType_ST) ||
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(request->m_type == RubyRequestType_ATOMIC) ||
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(request->m_type == RubyRequestType_RMW_Read) ||
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(request->m_type == RubyRequestType_RMW_Write) ||
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(request->m_type == RubyRequestType_Load_Linked) ||
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(request->m_type == RubyRequestType_Store_Conditional) ||
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(request->m_type == RubyRequestType_Locked_RMW_Read) ||
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(request->m_type == RubyRequestType_Locked_RMW_Write) ||
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(request->m_type == RubyRequestType_FLUSH));
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//
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// For Alpha, properly handle LL, SC, and write requests with respect to
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// locked cache blocks.
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//
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// Not valid for Network_test protocl
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//
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bool success = true;
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if(!m_usingNetworkTester)
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success = handleLlsc(address, request);
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if (request->m_type == RubyRequestType_Locked_RMW_Read) {
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m_controller->blockOnQueue(address, m_mandatory_q_ptr);
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} else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
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m_controller->unblock(address);
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}
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hitCallback(request, data, success, mach, externalHit,
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initialRequestTime, forwardRequestTime, firstResponseTime);
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}
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void
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Sequencer::readCallback(Addr address, DataBlock& data,
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bool externalHit, const MachineType mach,
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Cycles initialRequestTime,
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Cycles forwardRequestTime,
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Cycles firstResponseTime)
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{
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assert(address == makeLineAddress(address));
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assert(m_readRequestTable.count(makeLineAddress(address)));
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RequestTable::iterator i = m_readRequestTable.find(address);
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assert(i != m_readRequestTable.end());
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SequencerRequest* request = i->second;
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m_readRequestTable.erase(i);
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markRemoved();
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assert((request->m_type == RubyRequestType_LD) ||
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(request->m_type == RubyRequestType_IFETCH));
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hitCallback(request, data, true, mach, externalHit,
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initialRequestTime, forwardRequestTime, firstResponseTime);
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}
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void
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Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
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bool llscSuccess,
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const MachineType mach, const bool externalHit,
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const Cycles initialRequestTime,
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const Cycles forwardRequestTime,
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const Cycles firstResponseTime)
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{
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warn_once("Replacement policy updates recently became the responsibility "
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"of SLICC state machines. Make sure to setMRU() near callbacks "
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"in .sm files!");
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PacketPtr pkt = srequest->pkt;
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Addr request_address(pkt->getAddr());
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RubyRequestType type = srequest->m_type;
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Cycles issued_time = srequest->issue_time;
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assert(curCycle() >= issued_time);
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Cycles total_latency = curCycle() - issued_time;
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// Profile the latency for all demand accesses.
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recordMissLatency(total_latency, type, mach, externalHit, issued_time,
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initialRequestTime, forwardRequestTime,
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firstResponseTime, curCycle());
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DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
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curTick(), m_version, "Seq",
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llscSuccess ? "Done" : "SC_Failed", "", "",
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printAddress(request_address), total_latency);
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// update the data unless it is a non-data-carrying flush
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if (RubySystem::getWarmupEnabled()) {
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data.setData(pkt->getConstPtr<uint8_t>(),
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getOffset(request_address), pkt->getSize());
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} else if (!pkt->isFlush()) {
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if ((type == RubyRequestType_LD) ||
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(type == RubyRequestType_IFETCH) ||
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(type == RubyRequestType_RMW_Read) ||
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(type == RubyRequestType_Locked_RMW_Read) ||
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(type == RubyRequestType_Load_Linked)) {
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memcpy(pkt->getPtr<uint8_t>(),
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data.getData(getOffset(request_address), pkt->getSize()),
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pkt->getSize());
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DPRINTF(RubySequencer, "read data %s\n", data);
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} else {
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data.setData(pkt->getConstPtr<uint8_t>(),
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getOffset(request_address), pkt->getSize());
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DPRINTF(RubySequencer, "set data %s\n", data);
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}
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}
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// If using the RubyTester, update the RubyTester sender state's
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// subBlock with the recieved data. The tester will later access
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// this state.
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if (m_usingRubyTester) {
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DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n",
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pkt->cmdString(), pkt->getAddr());
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RubyTester::SenderState* testerSenderState =
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pkt->findNextSenderState<RubyTester::SenderState>();
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assert(testerSenderState);
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testerSenderState->subBlock.mergeFrom(data);
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}
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delete srequest;
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RubySystem *rs = m_ruby_system;
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|
if (RubySystem::getWarmupEnabled()) {
|
|
assert(pkt->req);
|
|
delete pkt->req;
|
|
delete pkt;
|
|
rs->m_cache_recorder->enqueueNextFetchRequest();
|
|
} else if (RubySystem::getCooldownEnabled()) {
|
|
delete pkt;
|
|
rs->m_cache_recorder->enqueueNextFlushRequest();
|
|
} else {
|
|
ruby_hit_callback(pkt);
|
|
testDrainComplete();
|
|
}
|
|
}
|
|
|
|
bool
|
|
Sequencer::empty() const
|
|
{
|
|
return m_writeRequestTable.empty() && m_readRequestTable.empty();
|
|
}
|
|
|
|
RequestStatus
|
|
Sequencer::makeRequest(PacketPtr pkt)
|
|
{
|
|
if (m_outstanding_count >= m_max_outstanding_requests) {
|
|
return RequestStatus_BufferFull;
|
|
}
|
|
|
|
RubyRequestType primary_type = RubyRequestType_NULL;
|
|
RubyRequestType secondary_type = RubyRequestType_NULL;
|
|
|
|
if (pkt->isLLSC()) {
|
|
//
|
|
// Alpha LL/SC instructions need to be handled carefully by the cache
|
|
// coherence protocol to ensure they follow the proper semantics. In
|
|
// particular, by identifying the operations as atomic, the protocol
|
|
// should understand that migratory sharing optimizations should not
|
|
// be performed (i.e. a load between the LL and SC should not steal
|
|
// away exclusive permission).
|
|
//
|
|
if (pkt->isWrite()) {
|
|
DPRINTF(RubySequencer, "Issuing SC\n");
|
|
primary_type = RubyRequestType_Store_Conditional;
|
|
} else {
|
|
DPRINTF(RubySequencer, "Issuing LL\n");
|
|
assert(pkt->isRead());
|
|
primary_type = RubyRequestType_Load_Linked;
|
|
}
|
|
secondary_type = RubyRequestType_ATOMIC;
|
|
} else if (pkt->req->isLockedRMW()) {
|
|
//
|
|
// x86 locked instructions are translated to store cache coherence
|
|
// requests because these requests should always be treated as read
|
|
// exclusive operations and should leverage any migratory sharing
|
|
// optimization built into the protocol.
|
|
//
|
|
if (pkt->isWrite()) {
|
|
DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
|
|
primary_type = RubyRequestType_Locked_RMW_Write;
|
|
} else {
|
|
DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
|
|
assert(pkt->isRead());
|
|
primary_type = RubyRequestType_Locked_RMW_Read;
|
|
}
|
|
secondary_type = RubyRequestType_ST;
|
|
} else {
|
|
if (pkt->isRead()) {
|
|
if (pkt->req->isInstFetch()) {
|
|
primary_type = secondary_type = RubyRequestType_IFETCH;
|
|
} else {
|
|
bool storeCheck = false;
|
|
// only X86 need the store check
|
|
if (system->getArch() == Arch::X86ISA) {
|
|
uint32_t flags = pkt->req->getFlags();
|
|
storeCheck = flags &
|
|
(X86ISA::StoreCheck << X86ISA::FlagShift);
|
|
}
|
|
if (storeCheck) {
|
|
primary_type = RubyRequestType_RMW_Read;
|
|
secondary_type = RubyRequestType_ST;
|
|
} else {
|
|
primary_type = secondary_type = RubyRequestType_LD;
|
|
}
|
|
}
|
|
} else if (pkt->isWrite()) {
|
|
//
|
|
// Note: M5 packets do not differentiate ST from RMW_Write
|
|
//
|
|
primary_type = secondary_type = RubyRequestType_ST;
|
|
} else if (pkt->isFlush()) {
|
|
primary_type = secondary_type = RubyRequestType_FLUSH;
|
|
} else {
|
|
panic("Unsupported ruby packet type\n");
|
|
}
|
|
}
|
|
|
|
RequestStatus status = insertRequest(pkt, primary_type);
|
|
if (status != RequestStatus_Ready)
|
|
return status;
|
|
|
|
issueRequest(pkt, secondary_type);
|
|
|
|
// TODO: issue hardware prefetches here
|
|
return RequestStatus_Issued;
|
|
}
|
|
|
|
void
|
|
Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
|
|
{
|
|
assert(pkt != NULL);
|
|
ContextID proc_id = pkt->req->hasContextId() ?
|
|
pkt->req->contextId() : InvalidContextID;
|
|
|
|
// If valid, copy the pc to the ruby request
|
|
Addr pc = 0;
|
|
if (pkt->req->hasPC()) {
|
|
pc = pkt->req->getPC();
|
|
}
|
|
|
|
// check if the packet has data as for example prefetch and flush
|
|
// requests do not
|
|
std::shared_ptr<RubyRequest> msg =
|
|
std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(),
|
|
pkt->isFlush() ?
|
|
nullptr : pkt->getPtr<uint8_t>(),
|
|
pkt->getSize(), pc, secondary_type,
|
|
RubyAccessMode_Supervisor, pkt,
|
|
PrefetchBit_No, proc_id);
|
|
|
|
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
|
|
curTick(), m_version, "Seq", "Begin", "", "",
|
|
printAddress(msg->getPhysicalAddress()),
|
|
RubyRequestType_to_string(secondary_type));
|
|
|
|
// The Sequencer currently assesses instruction and data cache hit latency
|
|
// for the top-level caches at the beginning of a memory access.
|
|
// TODO: Eventually, this latency should be moved to represent the actual
|
|
// cache access latency portion of the memory access. This will require
|
|
// changing cache controller protocol files to assess the latency on the
|
|
// access response path.
|
|
Cycles latency(0); // Initialize to zero to catch misconfigured latency
|
|
if (secondary_type == RubyRequestType_IFETCH)
|
|
latency = m_inst_cache_hit_latency;
|
|
else
|
|
latency = m_data_cache_hit_latency;
|
|
|
|
// Send the message to the cache controller
|
|
assert(latency > 0);
|
|
|
|
assert(m_mandatory_q_ptr != NULL);
|
|
m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(latency));
|
|
}
|
|
|
|
template <class KEY, class VALUE>
|
|
std::ostream &
|
|
operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
|
|
{
|
|
auto i = map.begin();
|
|
auto end = map.end();
|
|
|
|
out << "[";
|
|
for (; i != end; ++i)
|
|
out << " " << i->first << "=" << i->second;
|
|
out << " ]";
|
|
|
|
return out;
|
|
}
|
|
|
|
void
|
|
Sequencer::print(ostream& out) const
|
|
{
|
|
out << "[Sequencer: " << m_version
|
|
<< ", outstanding requests: " << m_outstanding_count
|
|
<< ", read request table: " << m_readRequestTable
|
|
<< ", write request table: " << m_writeRequestTable
|
|
<< "]";
|
|
}
|
|
|
|
// this can be called from setState whenever coherence permissions are
|
|
// upgraded when invoked, coherence violations will be checked for the
|
|
// given block
|
|
void
|
|
Sequencer::checkCoherence(Addr addr)
|
|
{
|
|
#ifdef CHECK_COHERENCE
|
|
m_ruby_system->checkGlobalCoherenceInvariant(addr);
|
|
#endif
|
|
}
|
|
|
|
void
|
|
Sequencer::recordRequestType(SequencerRequestType requestType) {
|
|
DPRINTF(RubyStats, "Recorded statistic: %s\n",
|
|
SequencerRequestType_to_string(requestType));
|
|
}
|
|
|
|
|
|
void
|
|
Sequencer::evictionCallback(Addr address)
|
|
{
|
|
ruby_eviction_callback(address);
|
|
}
|
|
|
|
void
|
|
Sequencer::regStats()
|
|
{
|
|
m_store_waiting_on_load
|
|
.name(name() + ".store_waiting_on_load")
|
|
.desc("Number of times a store aliased with a pending load")
|
|
.flags(Stats::nozero);
|
|
m_store_waiting_on_store
|
|
.name(name() + ".store_waiting_on_store")
|
|
.desc("Number of times a store aliased with a pending store")
|
|
.flags(Stats::nozero);
|
|
m_load_waiting_on_load
|
|
.name(name() + ".load_waiting_on_load")
|
|
.desc("Number of times a load aliased with a pending load")
|
|
.flags(Stats::nozero);
|
|
m_load_waiting_on_store
|
|
.name(name() + ".load_waiting_on_store")
|
|
.desc("Number of times a load aliased with a pending store")
|
|
.flags(Stats::nozero);
|
|
|
|
// These statistical variables are not for display.
|
|
// The profiler will collate these across different
|
|
// sequencers and display those collated statistics.
|
|
m_outstandReqHist.init(10);
|
|
m_latencyHist.init(10);
|
|
m_hitLatencyHist.init(10);
|
|
m_missLatencyHist.init(10);
|
|
|
|
for (int i = 0; i < RubyRequestType_NUM; i++) {
|
|
m_typeLatencyHist.push_back(new Stats::Histogram());
|
|
m_typeLatencyHist[i]->init(10);
|
|
|
|
m_hitTypeLatencyHist.push_back(new Stats::Histogram());
|
|
m_hitTypeLatencyHist[i]->init(10);
|
|
|
|
m_missTypeLatencyHist.push_back(new Stats::Histogram());
|
|
m_missTypeLatencyHist[i]->init(10);
|
|
}
|
|
|
|
for (int i = 0; i < MachineType_NUM; i++) {
|
|
m_hitMachLatencyHist.push_back(new Stats::Histogram());
|
|
m_hitMachLatencyHist[i]->init(10);
|
|
|
|
m_missMachLatencyHist.push_back(new Stats::Histogram());
|
|
m_missMachLatencyHist[i]->init(10);
|
|
|
|
m_IssueToInitialDelayHist.push_back(new Stats::Histogram());
|
|
m_IssueToInitialDelayHist[i]->init(10);
|
|
|
|
m_InitialToForwardDelayHist.push_back(new Stats::Histogram());
|
|
m_InitialToForwardDelayHist[i]->init(10);
|
|
|
|
m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram());
|
|
m_ForwardToFirstResponseDelayHist[i]->init(10);
|
|
|
|
m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram());
|
|
m_FirstResponseToCompletionDelayHist[i]->init(10);
|
|
}
|
|
|
|
for (int i = 0; i < RubyRequestType_NUM; i++) {
|
|
m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>());
|
|
m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>());
|
|
|
|
for (int j = 0; j < MachineType_NUM; j++) {
|
|
m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram());
|
|
m_hitTypeMachLatencyHist[i][j]->init(10);
|
|
|
|
m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram());
|
|
m_missTypeMachLatencyHist[i][j]->init(10);
|
|
}
|
|
}
|
|
}
|