gem5/src
Gabe Black 15f57bd7cb Fix immediate shifts. Implement register shifts.
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extra : convert_revision : 0b83422ad3c190021e46cada07e64d8d57d29859
2007-07-24 15:10:20 -07:00
..
arch Fix immediate shifts. Implement register shifts. 2007-07-24 15:10:20 -07:00
base Merge Gabe's changes with mine. 2007-07-22 10:40:45 -04:00
cpu o3cpu build for mips 2007-06-28 05:30:46 -04:00
dev Fix & tweak DPRINTFs for tracediff w/new cache code. 2007-07-14 11:48:30 -07:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Change getDeviceAddressRanges to use bool for snoop arg. 2007-05-21 23:36:09 -07:00
mem Fix & tweak DPRINTFs for tracediff w/new cache code. 2007-07-14 11:48:30 -07:00
python Add a function to get a SimObject's memory mode and rework 2007-06-10 13:52:21 -07:00
sim Make name, isMachineCheckFault, and isAlignmentFault const. 2007-07-18 16:09:00 -07:00
unittest Quick program to time how long ccprintf takes to write 2007-02-07 22:02:09 -08:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript Don't go over 80 chars per line 2007-06-20 08:12:10 -07:00