gem5/arch/mips/isa/base.isa
Korey Sewell 7c9ea671af file name changes ... minor ISA changes
arch/mips/isa/base.isa:
    restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
    add c++ emacs header
arch/mips/isa/formats/branch.isa:
    added branch likely format
arch/mips/isa/formats/int.isa:
    small change to python code

--HG--
extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
2006-02-16 02:39:46 -05:00

64 lines
1.7 KiB
C++

// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// Base class for MIPS instructions, and some support functions
//
//Outputs to decoder.hh
output header {{
/**
* Base class for all SPARC static instructions.
*/
class MipsStaticInst : public StaticInst<MIPSISA>
{
protected:
// Constructor.
MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
: StaticInst<SPARCISA>(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
//Ouputs to decoder.cc
output decoder {{
std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if(_numSrcRegs > 0)
{
printReg(ss, _srcRegIdx[0]);
}
if(_numSrcRegs > 1)
{
ss << ",";
printReg(ss, _srcRegIdx[1]);
}
// just print the first dest... if there's a second one,
// it's generally implicit
if(_numDestRegs > 0)
{
if(_numSrcRegs > 0)
ss << ",";
printReg(ss, _destRegIdx[0]);
}
return ss.str();
}
}};