351 lines
13 KiB
C++
351 lines
13 KiB
C++
/*
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* Copyright (c) 2003-2006, 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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/*
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* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/miscregfile.hh"
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#include "arch/x86/tlb.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "sim/serialize.hh"
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using namespace X86ISA;
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using namespace std;
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class Checkpoint;
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void MiscRegFile::clear()
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{
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// Blank everything. 0 might not be an appropriate value for some things,
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// but it is for most.
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memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
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regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
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regVal[MISCREG_DR7] = 1 << 10;
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}
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MiscReg MiscRegFile::readRegNoEffect(MiscRegIndex miscReg)
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{
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// Make sure we're not dealing with an illegal control register.
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// Instructions should filter out these indexes, and nothing else should
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// attempt to read them directly.
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assert( miscReg != MISCREG_CR1 &&
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!(miscReg > MISCREG_CR4 &&
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miscReg < MISCREG_CR8) &&
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!(miscReg > MISCREG_CR8 &&
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miscReg <= MISCREG_CR15));
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return regVal[miscReg];
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}
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MiscReg MiscRegFile::readReg(MiscRegIndex miscReg, ThreadContext * tc)
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{
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if (miscReg == MISCREG_TSC) {
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return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
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}
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return readRegNoEffect(miscReg);
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}
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void MiscRegFile::setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val)
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{
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// Make sure we're not dealing with an illegal control register.
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// Instructions should filter out these indexes, and nothing else should
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// attempt to write to them directly.
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assert( miscReg != MISCREG_CR1 &&
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!(miscReg > MISCREG_CR4 &&
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miscReg < MISCREG_CR8) &&
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!(miscReg > MISCREG_CR8 &&
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miscReg <= MISCREG_CR15));
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regVal[miscReg] = val;
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}
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void MiscRegFile::setReg(MiscRegIndex miscReg,
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const MiscReg &val, ThreadContext * tc)
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{
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MiscReg newVal = val;
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switch(miscReg)
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{
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case MISCREG_CR0:
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{
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CR0 toggled = regVal[miscReg] ^ val;
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CR0 newCR0 = val;
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Efer efer = regVal[MISCREG_EFER];
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HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
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if (toggled.pg && efer.lme) {
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if (newCR0.pg) {
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//Turning on long mode
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efer.lma = 1;
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m5reg.mode = LongMode;
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regVal[MISCREG_EFER] = efer;
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} else {
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//Turning off long mode
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efer.lma = 0;
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m5reg.mode = LegacyMode;
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regVal[MISCREG_EFER] = efer;
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}
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}
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// Figure out what submode we're in.
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if (m5reg.mode == LongMode) {
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SegAttr csAttr = regVal[MISCREG_CS_ATTR];
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if (csAttr.longMode)
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m5reg.submode = SixtyFourBitMode;
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else
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m5reg.submode = CompatabilityMode;
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} else {
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if (newCR0.pe) {
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RFLAGS rflags = regVal[MISCREG_RFLAGS];
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if (rflags.vm)
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m5reg.submode = Virtual8086Mode;
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else
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m5reg.submode = ProtectedMode;
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} else {
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m5reg.submode = RealMode;
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}
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}
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regVal[MISCREG_M5_REG] = m5reg;
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if (toggled.pg) {
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tc->getITBPtr()->invalidateAll();
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tc->getDTBPtr()->invalidateAll();
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}
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//This must always be 1.
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newCR0.et = 1;
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newVal = newCR0;
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}
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break;
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case MISCREG_CR2:
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break;
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case MISCREG_CR3:
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tc->getITBPtr()->invalidateNonGlobal();
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tc->getDTBPtr()->invalidateNonGlobal();
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break;
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case MISCREG_CR4:
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{
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CR4 toggled = regVal[miscReg] ^ val;
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if (toggled.pae || toggled.pse || toggled.pge) {
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tc->getITBPtr()->invalidateAll();
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tc->getDTBPtr()->invalidateAll();
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}
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}
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break;
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case MISCREG_CR8:
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break;
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case MISCREG_CS_ATTR:
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{
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SegAttr toggled = regVal[miscReg] ^ val;
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SegAttr newCSAttr = val;
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HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
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if (toggled.longMode) {
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if (newCSAttr.longMode) {
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if (m5reg.mode == LongMode)
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m5reg.submode = SixtyFourBitMode;
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regVal[MISCREG_ES_EFF_BASE] = 0;
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regVal[MISCREG_CS_EFF_BASE] = 0;
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regVal[MISCREG_SS_EFF_BASE] = 0;
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regVal[MISCREG_DS_EFF_BASE] = 0;
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} else {
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if (m5reg.mode == LongMode)
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m5reg.submode = CompatabilityMode;
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regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
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regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
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regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
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regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
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}
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}
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m5reg.cpl = newCSAttr.dpl;
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regVal[MISCREG_M5_REG] = m5reg;
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}
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break;
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// These segments always actually use their bases, or in other words
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// their effective bases must stay equal to their actual bases.
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case MISCREG_FS_BASE:
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case MISCREG_GS_BASE:
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case MISCREG_HS_BASE:
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case MISCREG_TSL_BASE:
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case MISCREG_TSG_BASE:
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case MISCREG_TR_BASE:
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case MISCREG_IDTR_BASE:
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regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
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break;
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// These segments ignore their bases in 64 bit mode.
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// their effective bases must stay equal to their actual bases.
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case MISCREG_ES_BASE:
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case MISCREG_CS_BASE:
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case MISCREG_SS_BASE:
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case MISCREG_DS_BASE:
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{
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Efer efer = regVal[MISCREG_EFER];
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SegAttr csAttr = regVal[MISCREG_CS_ATTR];
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if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
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regVal[MISCREG_SEG_EFF_BASE(miscReg -
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MISCREG_SEG_BASE_BASE)] = val;
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}
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break;
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case MISCREG_TSC:
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regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
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return;
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case MISCREG_DR0:
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case MISCREG_DR1:
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case MISCREG_DR2:
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case MISCREG_DR3:
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/* These should eventually set up breakpoints. */
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break;
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case MISCREG_DR4:
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miscReg = MISCREG_DR6;
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/* Fall through to have the same effects as DR6. */
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case MISCREG_DR6:
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{
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DR6 dr6 = regVal[MISCREG_DR6];
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DR6 newDR6 = val;
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dr6.b0 = newDR6.b0;
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dr6.b1 = newDR6.b1;
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dr6.b2 = newDR6.b2;
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dr6.b3 = newDR6.b3;
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dr6.bd = newDR6.bd;
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dr6.bs = newDR6.bs;
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dr6.bt = newDR6.bt;
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newVal = dr6;
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}
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break;
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case MISCREG_DR5:
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miscReg = MISCREG_DR7;
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/* Fall through to have the same effects as DR7. */
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case MISCREG_DR7:
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{
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DR7 dr7 = regVal[MISCREG_DR7];
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DR7 newDR7 = val;
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dr7.l0 = newDR7.l0;
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dr7.g0 = newDR7.g0;
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if (dr7.l0 || dr7.g0) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 0. */
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}
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dr7.l1 = newDR7.l1;
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dr7.g1 = newDR7.g1;
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if (dr7.l1 || dr7.g1) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 1. */
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}
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dr7.l2 = newDR7.l2;
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dr7.g2 = newDR7.g2;
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if (dr7.l2 || dr7.g2) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 2. */
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}
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dr7.l3 = newDR7.l3;
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dr7.g3 = newDR7.g3;
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if (dr7.l3 || dr7.g3) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 3. */
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}
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dr7.gd = newDR7.gd;
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dr7.rw0 = newDR7.rw0;
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dr7.len0 = newDR7.len0;
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dr7.rw1 = newDR7.rw1;
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dr7.len1 = newDR7.len1;
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dr7.rw2 = newDR7.rw2;
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dr7.len2 = newDR7.len2;
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dr7.rw3 = newDR7.rw3;
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dr7.len3 = newDR7.len3;
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}
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break;
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default:
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break;
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}
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setRegNoEffect(miscReg, newVal);
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}
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void MiscRegFile::serialize(std::ostream & os)
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{
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SERIALIZE_ARRAY(regVal, NumMiscRegs);
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}
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void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
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{
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UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
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}
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