8909843a76
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
645 lines
73 KiB
Plaintext
645 lines
73 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.043695 # Number of seconds simulated
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sim_ticks 1043695077500 # Number of ticks simulated
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final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 877071 # Simulator instruction rate (inst/s)
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host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1431720298 # Simulator tick rate (ticks/s)
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host_mem_usage 317788 # Number of bytes of host memory used
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host_seconds 728.98 # Real time elapsed on the host
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sim_insts 639366786 # Number of instructions simulated
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sim_ops 785501034 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.walker.walks 0 # Table walker walks requested
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system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.walker.walks 0 # Table walker walks requested
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system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 673 # Number of system calls
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system.cpu.numCycles 2087390155 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 639366786 # Number of instructions committed
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system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
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system.cpu.num_func_calls 37261296 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
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system.cpu.num_int_insts 682251400 # number of integer instructions
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system.cpu.num_fp_insts 24239771 # number of float instructions
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system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read
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system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
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system.cpu.num_mem_refs 381221435 # number of memory refs
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system.cpu.num_load_insts 252240938 # Number of load instructions
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system.cpu.num_store_insts 128980497 # Number of store instructions
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system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
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system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles
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system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
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system.cpu.Branches 137364859 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction
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system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
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system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
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system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 788730743 # Class of executed instruction
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system.cpu.dcache.tags.replacements 778046 # number of replacements
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system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
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system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
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system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses
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system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits
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system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits
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system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 378498833 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 782143 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 91561 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 8769 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 643367691 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 10208 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 256932 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 7430286 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 8438 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 490970 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 499408 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 91561 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 8438 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 494200 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 502638 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 8438 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 494200 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 502638 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1770 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 221849 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 223619 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1770 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 287942 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 289712 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 289712 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92997000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647316500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 11740313500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469929500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3469929500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 92997000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 15117246000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 92997000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 15117246000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 91561 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.173393 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311228 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.309282 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173393 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368145 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.365636 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1770 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221849 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 223619 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1770 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 287942 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 223619 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 223619 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 355811 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 355811 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|