gem5/src/mem/cache
Steve Reinhardt 19c367fa8f Fix subtle cache bug where read could return stale data
if a prior write miss arrived while an even earlier
read miss was still outstanding.

--HG--
extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
2008-03-15 05:03:55 -07:00
..
prefetch Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
tags Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
base.cc Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
base.hh Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
BaseCache.py DMA: Add IOCache and fix bus bridge to optionally only send requests one 2007-08-10 16:14:01 -04:00
blk.cc Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
blk.hh Revamp cache timing access mshr check to make stats sane again. 2008-02-26 22:03:28 -08:00
builder.cc Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
cache.cc Get rid of coherence protocol object. 2007-06-27 20:54:13 -07:00
cache.hh Cache: better comments particularly regarding writeback situation. 2008-02-26 20:17:26 -08:00
cache_impl.hh Fix subtle cache bug where read could return stale data 2008-03-15 05:03:55 -07:00
mshr.cc Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
mshr.hh Rename cache files for brevity and consistency with rest of tree. 2008-02-10 14:15:42 -08:00
mshr_queue.cc Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
mshr_queue.hh Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
SConscript Rename cache files for brevity and consistency with rest of tree. 2008-02-10 14:15:42 -08:00