74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
1453 lines
168 KiB
Text
1453 lines
168 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.859220 # Number of seconds simulated
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sim_ticks 1859219766000 # Number of ticks simulated
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final_tick 1859219766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 91264 # Simulator instruction rate (inst/s)
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host_op_rate 91264 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3202546943 # Simulator tick rate (ticks/s)
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host_mem_usage 310256 # Number of bytes of host memory used
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host_seconds 580.54 # Real time elapsed on the host
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sim_insts 52982774 # Number of instructions simulated
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sim_ops 52982774 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24879168 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28495424 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388737 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 445241 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 518480 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13381510 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 1426560 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 15326550 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 518480 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 518480 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4042229 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4042229 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4042229 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 518480 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13381510 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1426560 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19368779 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 445241 # Total number of read requests seen
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system.physmem.writeReqs 117428 # Total number of write requests seen
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system.physmem.cpureqs 562841 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 28495424 # Total number of bytes read from memory
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system.physmem.bytesWritten 7515392 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28495424 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7515392 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 28229 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 27975 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 28436 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 28026 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 27802 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 27225 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 27248 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 27297 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 27658 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 27398 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 27928 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 27536 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 28226 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 28326 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 28320 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 7499 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 7946 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 7517 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 6679 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 6762 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 6683 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 7096 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 6802 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 7320 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 6981 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 7118 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 7875 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 8048 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 7826 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
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system.physmem.totGap 1859214351000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 445241 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 117428 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 330939 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 63289 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 19437 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 6277 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3346 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3045 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1556 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1541 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1493 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1425 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 2022 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 2332 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2208 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 1206 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 458 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 226 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 109 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 3744 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4808 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 5100 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 1362 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 37468 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 960.941176 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 233.799958 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 2437.428145 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-67 12972 34.62% 34.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-131 5555 14.83% 49.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-195 3417 9.12% 58.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-259 2277 6.08% 64.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-323 1679 4.48% 69.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-387 1428 3.81% 72.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-451 991 2.64% 75.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-515 802 2.14% 77.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-579 632 1.69% 79.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-643 550 1.47% 80.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-707 599 1.60% 82.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-771 534 1.43% 83.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-835 276 0.74% 84.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-899 243 0.65% 85.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-963 192 0.51% 85.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1027 257 0.69% 86.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1091 103 0.27% 86.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1155 109 0.29% 87.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1283 145 0.39% 87.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1347 226 0.60% 88.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1411 117 0.31% 88.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1475 450 1.20% 89.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1539 603 1.61% 91.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1603 73 0.19% 91.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1667 37 0.10% 91.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1731 34 0.09% 91.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1795 78 0.21% 91.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1859 30 0.08% 92.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920-1923 11 0.03% 92.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1987 8 0.02% 92.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2051 42 0.11% 92.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112-2115 24 0.06% 92.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240-2243 2 0.01% 92.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2371 6 0.02% 92.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.40% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.40% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3203 2 0.01% 92.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.47% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3840-3843 3 0.01% 92.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3904-3907 2 0.01% 92.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4096-4099 2 0.01% 92.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4608-4611 1 0.00% 92.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4864-4867 2 0.01% 92.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.55% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.55% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::5056-5059 1 0.00% 92.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.56% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.56% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.56% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5891 2 0.01% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5955 1 0.00% 92.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6403 2 0.01% 92.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6531 1 0.00% 92.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7939 1 0.00% 92.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8067 3 0.01% 92.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8195 2434 6.50% 99.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14720-14723 2 0.01% 99.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14912-14915 3 0.01% 99.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16512-16515 7 0.02% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16768-16771 2 0.01% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17280-17283 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 37468 # Bytes accessed per row activation
|
|
system.physmem.totQLat 6065400750 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 13430024500 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 2225905000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 5138718750 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 13624.57 # Average queueing delay per request
|
|
system.physmem.avgBankLat 11542.99 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 30167.56 # Average memory access latency
|
|
system.physmem.avgRdBW 15.33 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 15.33 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 0.15 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.01 # Average read queue length over time
|
|
system.physmem.avgWrQLen 11.93 # Average write queue length over time
|
|
system.physmem.readRowHits 430163 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 94965 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 96.63 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3304277.21 # Average gap between requests
|
|
system.membus.throughput 19411663 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 296022 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 295937 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 117428 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 173 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 174 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 156790 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 156790 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 85 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884132 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917358 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.physmem.port 1008811 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1042037 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701760 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745908 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.physmem.port 36010816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 36054964 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 36054964 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 29876000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1541728249 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 108500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3763624798 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 376221741 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.replacements 41685 # number of replacements
|
|
system.iocache.tagsinuse 1.261712 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1709369770000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.occ_blocks::tsunami.ide 1.261712 # Average occupied blocks per requestor
|
|
system.iocache.occ_percent::tsunami.ide 0.078857 # Average percentage of cache occupancy
|
|
system.iocache.occ_percent::total 0.078857 # Average percentage of cache occupancy
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::tsunami.ide 10471007269 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 10471007269 # number of WriteReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 10492350152 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 10492350152 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 10492350152 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 10492350152 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251997.672049 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 251997.672049 # average WriteReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 251464.353553 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 251464.353553 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 273612 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 27136 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 10.082989 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8309607278 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 8309607278 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 8321953411 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 8321953411 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 8321953411 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 8321953411 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199980.922170 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 199980.922170 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.branchPred.lookups 13839600 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 11609173 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 399191 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9510547 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5805743 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 61.045311 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 906368 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 39168 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9923550 # DTB read hits
|
|
system.cpu.dtb.read_misses 41274 # DTB read misses
|
|
system.cpu.dtb.read_acv 543 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 941562 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6598688 # DTB write hits
|
|
system.cpu.dtb.write_misses 10641 # DTB write misses
|
|
system.cpu.dtb.write_acv 411 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 338433 # DTB write accesses
|
|
system.cpu.dtb.data_hits 16522238 # DTB hits
|
|
system.cpu.dtb.data_misses 51915 # DTB misses
|
|
system.cpu.dtb.data_acv 954 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1279995 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1308614 # ITB hits
|
|
system.cpu.itb.fetch_misses 36742 # ITB misses
|
|
system.cpu.itb.fetch_acv 1058 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1345356 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 120145786 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 28059248 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 70722559 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 13839600 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 6712111 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 13258692 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1994060 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 38168658 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 32286 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 254324 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 364483 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 8570347 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 266679 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 81425482 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.868556 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.211321 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 68166790 83.72% 83.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 854823 1.05% 84.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1706158 2.10% 86.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 819634 1.01% 87.87% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2757548 3.39% 91.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 561946 0.69% 91.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 649151 0.80% 92.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1013766 1.25% 93.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 4895666 6.01% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 81425482 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.115190 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.588640 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 29284437 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 37811275 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 12102091 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 982484 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1245194 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 583690 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 42726 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 69419384 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 129751 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1245194 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 30419678 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 14066203 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 19996824 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 11337239 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 4360342 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 65632842 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 7067 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 503743 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 1590486 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 43821413 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 79676034 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 79196502 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 479532 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38182467 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 5638938 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1682867 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 239802 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12252220 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 10440672 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 6902467 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1316833 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 861587 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 58171642 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2051698 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 56802904 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 100593 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 6885118 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 3554028 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1390714 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 81425482 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.697606 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.359574 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 56719527 69.66% 69.66% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 10865996 13.34% 83.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 5212450 6.40% 89.40% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 3349939 4.11% 93.52% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 2634366 3.24% 96.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1460723 1.79% 98.55% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 752656 0.92% 99.47% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 333424 0.41% 99.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 96401 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 81425482 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 93250 11.76% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 372953 47.03% 58.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 326761 41.21% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 38720727 68.17% 68.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 61725 0.11% 68.29% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 10357561 18.23% 86.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6677285 11.76% 98.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 56802904 # Type of FU issued
|
|
system.cpu.iq.rate 0.472783 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 792964 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.013960 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 195231977 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 66785301 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55558093 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 692869 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 336906 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 327947 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 57227049 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 361533 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 597916 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1347952 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3269 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 524235 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 17914 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 199705 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1245194 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 10207267 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 699182 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 63757422 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 685568 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 10440672 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 6902467 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1806514 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 512114 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 18348 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 200766 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 410779 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 611545 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 56334870 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 9992999 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 468033 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3534082 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 16617553 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 8923539 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6624554 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.468888 # Inst execution rate
|
|
system.cpu.iew.wb_sent 55999832 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 55886040 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 27701007 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 37529982 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.465152 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.738103 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 7465540 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 660984 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 567902 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 80180288 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.700591 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.629829 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 59372363 74.05% 74.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 8630775 10.76% 84.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4656269 5.81% 90.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2498281 3.12% 93.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1510890 1.88% 95.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 609736 0.76% 96.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 522635 0.65% 97.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 527296 0.66% 97.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 1852043 2.31% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 80180288 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 56173622 # Number of instructions committed
|
|
system.cpu.commit.committedOps 56173622 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15470952 # Number of memory references committed
|
|
system.cpu.commit.loads 9092720 # Number of loads committed
|
|
system.cpu.commit.membars 226359 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8440448 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52023156 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 740622 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 1852043 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 141717845 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 128525319 # The number of ROB writes
|
|
system.cpu.timesIdled 1192872 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 38720304 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 3598287306 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 52982774 # Number of Instructions Simulated
|
|
system.cpu.committedOps 52982774 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 52982774 # Number of Instructions Simulated
|
|
system.cpu.cpi 2.267639 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.267639 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.440987 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.440987 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 73877727 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 40299404 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 166073 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 167447 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1985193 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.iobus.throughput 1455318 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51150 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 2705756 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 378262152 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.throughput 112025274 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2118762 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2118660 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 840976 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 68 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 342524 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 300973 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020715 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3678751 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 5699466 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64659008 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143612852 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 208271860 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 208261812 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 17792 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2480878498 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1516366019 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2115023448 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.icache.replacements 1009685 # number of replacements
|
|
system.cpu.icache.tagsinuse 509.751691 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 7503411 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1010193 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 7.427700 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 25536785000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 509.751691 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.995609 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.995609 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 7503412 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7503412 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 7503412 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7503412 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 7503412 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7503412 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1066934 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1066934 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1066934 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1066934 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1066934 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1066934 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15003433992 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 15003433992 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 15003433992 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 15003433992 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 15003433992 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 15003433992 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 8570346 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 8570346 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 8570346 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 8570346 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 8570346 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 8570346 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124491 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.124491 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.124491 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.124491 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.124491 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.124491 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14062.195030 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14062.195030 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14062.195030 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14062.195030 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 6693 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 179 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 211 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.720379 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 179 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56516 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 56516 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 56516 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 56516 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 56516 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 56516 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010418 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1010418 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1010418 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1010418 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1010418 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1010418 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12286930976 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12286930976 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12286930976 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12286930976 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12286930976 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12286930976 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117897 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.117897 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.117897 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12160.245538 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12160.245538 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12160.245538 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12160.245538 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12160.245538 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12160.245538 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 338301 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 65341.966767 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2546946 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 403469 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 6.312619 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 5291618750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 53911.533514 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 5311.895957 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6118.537295 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.822625 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.081053 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.093361 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.997039 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 995233 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 827385 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1822618 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 840976 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 840976 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 185596 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 185596 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 995233 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1012981 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2008214 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 995233 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1012981 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2008214 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 273856 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 288920 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 115376 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 389232 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 404296 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 389232 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 404296 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1298626000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17151313000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18449939000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 262000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 23000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 23000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338142500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9338142500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1298626000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 26489455500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 27788081500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1298626000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 26489455500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 27788081500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010297 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1101241 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2111538 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 840976 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 840976 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 300972 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 300972 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1010297 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1402213 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2412510 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1010297 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1402213 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2412510 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014910 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248679 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.136829 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.546875 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.546875 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383345 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383345 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014910 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277584 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.167583 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014910 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277584 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.167583 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86207.249071 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62628.947330 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 63858.296414 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7485.714286 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7485.714286 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23000 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23000 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.611600 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.611600 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86207.249071 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68055.698144 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 68732.021835 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86207.249071 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68055.698144 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 68732.021835 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 75916 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 75916 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273856 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 288919 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389232 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 404295 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389232 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 404295 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1111091007 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13804931769 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14916022776 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 500532 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 500532 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7927592393 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7927592393 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1111091007 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21732524162 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 22843615169 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1111091007 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21732524162 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 22843615169 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333956500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333956500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882603500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882603500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216560000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216560000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136829 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.546875 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.546875 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383345 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383345 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.167583 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.167583 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73762.929496 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50409.455221 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51627.005410 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14300.914286 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14300.914286 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68710.931156 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68710.931156 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1401615 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.994565 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 11806786 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1402127 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 8.420625 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 25214000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.994565 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7200855 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7200855 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4204221 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4204221 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 185946 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 185946 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 215517 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 11405076 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 11405076 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 11405076 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 11405076 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1804057 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1804057 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1943787 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1943787 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22748 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3747844 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3747844 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3747844 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3747844 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39515383000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 39515383000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 75738860769 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 75738860769 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321949000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 321949000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 65000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 65000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 115254243769 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 115254243769 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 115254243769 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 115254243769 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9004912 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9004912 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6148008 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6148008 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208694 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 208694 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15152920 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15152920 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15152920 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15152920 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200341 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.200341 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316165 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.316165 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109002 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109002 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.247335 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.247335 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.247335 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.247335 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21903.622225 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 21903.622225 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38964.588594 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38964.588594 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14152.848602 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14152.848602 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16250 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16250 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30752.145439 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30752.145439 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 2955693 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 101444 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.136203 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 840976 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 840976 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719736 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 719736 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643409 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1643409 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5171 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5171 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2363145 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2363145 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2363145 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2363145 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084321 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1084321 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300378 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 300378 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17577 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17577 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1384699 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1384699 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1384699 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1384699 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26518641540 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26518641540 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11550001786 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11550001786 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 202636005 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 202636005 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 57000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 57000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38068643326 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 38068643326 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38068643326 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 38068643326 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424047000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424047000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997793498 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997793498 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421840498 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421840498 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120414 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120414 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048858 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084224 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084224 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091382 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091382 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24456.449280 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24456.449280 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38451.556992 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38451.556992 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11528.474996 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11528.474996 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14250 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14250 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1817988566000 97.78% 97.78% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 64092000 0.00% 97.79% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 554660500 0.03% 97.82% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 40611610500 2.18% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1859218929000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 191976 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1910
|
|
system.cpu.kern.mode_good::user 1740
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.326328 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29661883000 1.60% 1.60% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2771562000 0.15% 1.74% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1826785476000 98.26% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
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