4f430e9ab5
arch/mips/isa/bitfields.isa: add RS_SRL bitfield ...these must be set to 0 for a SRL instruction arch/mips/isa/decoder.isa: Make unimplemented instructions Fail instead of just Warn Edits to SRA & SRAV instructions Implement CFC1 instructions Unaligned Memory Access Support (Maybe Not fully functional yet) Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions) arch/mips/isa/formats/branch.isa: Fix disassembly arch/mips/isa/formats/int.isa: Add sign extend Immediate and zero extend Immediate to Int class. Probably a bit unnecessary in the long run since these manipulations could be done in the actually instruction instead of keep a int value arch/mips/isa/formats/mem.isa: Comment/Remove out split-memory access code... revisit this after SimpleCPU works arch/mips/isa/formats/unimp.isa: Add inst2string function to Unimplemented panic. PRints out the instruction binary to help in debuggin arch/mips/isa/formats/unknown.isa: define inst2string function , use in unknown disassembly and panic function arch/mips/isa/operands.isa: Make "Mem" default to a unsigned word since this is MIPS32 arch/mips/isa_traits.hh: change return values to 32 instead of 64 arch/mips/linux_process.cc: assign some syscalls to the right functions cpu/static_inst.hh: more debug functions for MIPS (these will be move to the mips directory soon) mem/page_table.cc: mem/page_table.hh: toward a better implementation for unaligned memory access mem/request.hh: NO ALIGN FAULT flag added to support unaligned memory access sim/syscall_emul.cc: additional SyscallVerbose comments --HG-- extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c
68 lines
1.6 KiB
C++
68 lines
1.6 KiB
C++
// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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def bitfield OPCODE <31:26>;
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def bitfield OPCODE_HI <31:29>;
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def bitfield OPCODE_LO <28:26>;
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def bitfield REGIMM <20:16>;
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def bitfield REGIMM_HI <20:19>;
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def bitfield REGIMM_LO <18:16>;
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def bitfield FUNCTION < 5: 0>;
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def bitfield FUNCTION_HI < 5: 3>;
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def bitfield FUNCTION_LO < 2: 0>;
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// Integer operate format
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def bitfield RT <20:16>;
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def bitfield RT_HI <20:19>;
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def bitfield RT_LO <18:16>;
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def bitfield RS <25:21>;
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def bitfield RS_MSB <25:25>;
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def bitfield RS_HI <25:24>;
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def bitfield RS_LO <23:21>;
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def bitfield RS_SRL <25:22>;
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def bitfield RD <15:11>;
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def bitfield INTIMM <15: 0>; // integer immediate (literal)
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// Floating-point operate format
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def bitfield FMT <25:21>;
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def bitfield FR <25:21>;
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def bitfield FT <20:16>;
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def bitfield FS <15:11>;
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def bitfield FD <10:6>;
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def bitfield CC <20:18>;
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def bitfield ND <17:17>;
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def bitfield TF <16:16>;
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def bitfield MOVCI <16:16>;
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def bitfield MOVCF <16:16>;
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def bitfield SRL <21:21>;
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def bitfield SRLV < 6: 6>;
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def bitfield SA <10: 6>;
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// CP0 Register Select
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def bitfield SEL < 2: 0>;
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// Interrupts
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def bitfield SC < 5: 5>;
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// Branch format
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def bitfield OFFSET <15: 0>; // displacement
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// Jmp format
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def bitfield JMPTARG <25: 0>;
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def bitfield HINT <10: 6>;
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def bitfield SYSCALLCODE <25: 6>;
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def bitfield TRAPCODE <15:13>;
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// M5 instructions
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def bitfield M5FUNC <7:0>;
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