0dd1f7f01a
This reduces the scope of those includes and makes it less likely for there to be a dependency loop. This also moves the hashing functions associated with ExtMachInst objects to be with the ExtMachInst definitions and out of utility.hh.
283 lines
8.1 KiB
C++
283 lines
8.1 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_TYPES_HH__
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#define __ARCH_ARM_TYPES_HH__
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#include "base/bitunion.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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namespace ArmISA
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{
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typedef uint32_t MachInst;
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BitUnion64(ExtMachInst)
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Bitfield<63, 56> newItstate;
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// ITSTATE bits
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Bitfield<55, 48> itstate;
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Bitfield<55, 52> itstateCond;
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Bitfield<51, 48> itstateMask;
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// FPSCR fields
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Bitfield<41, 40> fpscrStride;
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Bitfield<39, 37> fpscrLen;
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// Bitfields to select mode.
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Bitfield<36> thumb;
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Bitfield<35> bigThumb;
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// Made up bitfields that make life easier.
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Bitfield<33> sevenAndFour;
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Bitfield<32> isMisc;
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uint32_t instBits;
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// All the different types of opcode fields.
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Bitfield<27, 25> encoding;
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Bitfield<25> useImm;
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Bitfield<24, 21> opcode;
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Bitfield<24, 20> mediaOpcode;
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Bitfield<24> opcode24;
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Bitfield<24, 23> opcode24_23;
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Bitfield<23, 20> opcode23_20;
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Bitfield<23, 21> opcode23_21;
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Bitfield<20> opcode20;
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Bitfield<22> opcode22;
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Bitfield<19, 16> opcode19_16;
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Bitfield<19> opcode19;
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Bitfield<18> opcode18;
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Bitfield<15, 12> opcode15_12;
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Bitfield<15> opcode15;
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Bitfield<7, 4> miscOpcode;
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Bitfield<7,5> opc2;
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Bitfield<7> opcode7;
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Bitfield<6> opcode6;
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Bitfield<4> opcode4;
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Bitfield<31, 28> condCode;
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Bitfield<20> sField;
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Bitfield<19, 16> rn;
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Bitfield<15, 12> rd;
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Bitfield<15, 12> rt;
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Bitfield<11, 7> shiftSize;
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Bitfield<6, 5> shift;
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Bitfield<3, 0> rm;
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Bitfield<11, 8> rs;
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SubBitUnion(puswl, 24, 20)
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Bitfield<24> prepost;
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Bitfield<23> up;
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Bitfield<22> psruser;
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Bitfield<21> writeback;
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Bitfield<20> loadOp;
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EndSubBitUnion(puswl)
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Bitfield<24, 20> pubwl;
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Bitfield<7, 0> imm;
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Bitfield<11, 8> rotate;
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Bitfield<11, 0> immed11_0;
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Bitfield<7, 0> immed7_0;
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Bitfield<11, 8> immedHi11_8;
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Bitfield<3, 0> immedLo3_0;
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Bitfield<15, 0> regList;
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Bitfield<23, 0> offset;
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Bitfield<23, 0> immed23_0;
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Bitfield<11, 8> cpNum;
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Bitfield<18, 16> fn;
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Bitfield<14, 12> fd;
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Bitfield<3> fpRegImm;
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Bitfield<3, 0> fm;
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Bitfield<2, 0> fpImm;
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Bitfield<24, 20> punwl;
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Bitfield<7, 0> m5Func;
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// 16 bit thumb bitfields
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Bitfield<15, 13> topcode15_13;
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Bitfield<13, 11> topcode13_11;
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Bitfield<12, 11> topcode12_11;
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Bitfield<12, 10> topcode12_10;
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Bitfield<11, 9> topcode11_9;
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Bitfield<11, 8> topcode11_8;
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Bitfield<10, 9> topcode10_9;
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Bitfield<10, 8> topcode10_8;
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Bitfield<9, 6> topcode9_6;
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Bitfield<7> topcode7;
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Bitfield<7, 6> topcode7_6;
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Bitfield<7, 5> topcode7_5;
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Bitfield<7, 4> topcode7_4;
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Bitfield<3, 0> topcode3_0;
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// 32 bit thumb bitfields
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Bitfield<28, 27> htopcode12_11;
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Bitfield<26, 25> htopcode10_9;
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Bitfield<25> htopcode9;
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Bitfield<25, 24> htopcode9_8;
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Bitfield<25, 21> htopcode9_5;
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Bitfield<25, 20> htopcode9_4;
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Bitfield<24> htopcode8;
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Bitfield<24, 23> htopcode8_7;
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Bitfield<24, 22> htopcode8_6;
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Bitfield<24, 21> htopcode8_5;
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Bitfield<23> htopcode7;
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Bitfield<23, 21> htopcode7_5;
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Bitfield<22> htopcode6;
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Bitfield<22, 21> htopcode6_5;
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Bitfield<21, 20> htopcode5_4;
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Bitfield<20> htopcode4;
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Bitfield<19, 16> htrn;
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Bitfield<20> hts;
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Bitfield<15> ltopcode15;
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Bitfield<11, 8> ltopcode11_8;
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Bitfield<7, 6> ltopcode7_6;
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Bitfield<7, 4> ltopcode7_4;
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Bitfield<4> ltopcode4;
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Bitfield<11, 8> ltrd;
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Bitfield<11, 8> ltcoproc;
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EndBitUnion(ExtMachInst)
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// Shift types for ARM instructions
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enum ArmShiftType {
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LSL = 0,
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LSR,
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ASR,
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ROR
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};
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typedef uint64_t LargestRead;
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// Need to use 64 bits to make sure that read requests get handled properly
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typedef int RegContextParam;
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typedef int RegContextVal;
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//used in FP convert & round function
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enum ConvertType{
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SINGLE_TO_DOUBLE,
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SINGLE_TO_WORD,
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SINGLE_TO_LONG,
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DOUBLE_TO_SINGLE,
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DOUBLE_TO_WORD,
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DOUBLE_TO_LONG,
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LONG_TO_SINGLE,
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LONG_TO_DOUBLE,
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LONG_TO_WORD,
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LONG_TO_PS,
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WORD_TO_SINGLE,
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WORD_TO_DOUBLE,
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WORD_TO_LONG,
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WORD_TO_PS,
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PL_TO_SINGLE,
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PU_TO_SINGLE
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};
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//used in FP convert & round function
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enum RoundMode{
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RND_ZERO,
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RND_DOWN,
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RND_UP,
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RND_NEAREST
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};
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enum OperatingMode {
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MODE_USER = 16,
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MODE_FIQ = 17,
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MODE_IRQ = 18,
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MODE_SVC = 19,
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MODE_MON = 22,
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MODE_ABORT = 23,
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MODE_UNDEFINED = 27,
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MODE_SYSTEM = 31,
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MODE_MAXMODE = MODE_SYSTEM
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};
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static inline bool
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badMode(OperatingMode mode)
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{
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switch (mode) {
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case MODE_USER:
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case MODE_FIQ:
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case MODE_IRQ:
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case MODE_SVC:
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case MODE_MON:
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case MODE_ABORT:
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case MODE_UNDEFINED:
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case MODE_SYSTEM:
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return false;
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default:
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return true;
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}
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}
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struct CoreSpecific {
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// Empty for now on the ARM
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};
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} // namespace ArmISA
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namespace __hash_namespace {
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template<>
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struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
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size_t operator()(const ArmISA::ExtMachInst &emi) const {
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return hash<uint32_t>::operator()((uint32_t)emi);
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};
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};
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}
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#endif
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