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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Andreas Hansson df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes 
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.818071 # Number of seconds simulated
sim_ticks 2818071194500 # Number of ticks simulated
final_tick 2818071194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 294940 # Simulator instruction rate (inst/s)
host_op_rate 358127 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6587540433 # Simulator tick rate (ticks/s)
host_mem_usage 622484 # Number of bytes of host memory used
host_seconds 427.79 # Real time elapsed on the host
sim_insts 126171688 # Number of instructions simulated
sim_ops 153202470 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 666276 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4385696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 127360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1038980 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 6016 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 505600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 4227776 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10959048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 666276 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 127360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 505600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1299236 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8262336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
system.physmem.bytes_written::total 8279860 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 18864 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 69045 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1990 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 16235 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 94 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 7900 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 66059 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 180208 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 129099 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
system.physmem.num_writes::total 133480 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 236430 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1556276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 45194 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 368685 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 2135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 179413 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1500237 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3888847 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 236430 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 45194 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 179413 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 461037 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2931912 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2938130 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2931912 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 236430 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1562491 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 45194 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 368688 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 2135 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 179413 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1500237 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6826977 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 92280 # Number of read requests accepted
system.physmem.writeReqs 90311 # Number of write requests accepted
system.physmem.readBursts 92280 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 90311 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5901184 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 4736 # Total number of bytes read from write queue
system.physmem.bytesWritten 5694528 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5905860 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5779784 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 74 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 1313 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 2491 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 6033 # Per bank write bursts
system.physmem.perBankRdBursts::1 5793 # Per bank write bursts
system.physmem.perBankRdBursts::2 5545 # Per bank write bursts
system.physmem.perBankRdBursts::3 6032 # Per bank write bursts
system.physmem.perBankRdBursts::4 5564 # Per bank write bursts
system.physmem.perBankRdBursts::5 5452 # Per bank write bursts
system.physmem.perBankRdBursts::6 6124 # Per bank write bursts
system.physmem.perBankRdBursts::7 6804 # Per bank write bursts
system.physmem.perBankRdBursts::8 6414 # Per bank write bursts
system.physmem.perBankRdBursts::9 6339 # Per bank write bursts
system.physmem.perBankRdBursts::10 5684 # Per bank write bursts
system.physmem.perBankRdBursts::11 5101 # Per bank write bursts
system.physmem.perBankRdBursts::12 5267 # Per bank write bursts
system.physmem.perBankRdBursts::13 5451 # Per bank write bursts
system.physmem.perBankRdBursts::14 5288 # Per bank write bursts
system.physmem.perBankRdBursts::15 5315 # Per bank write bursts
system.physmem.perBankWrBursts::0 5413 # Per bank write bursts
system.physmem.perBankWrBursts::1 4989 # Per bank write bursts
system.physmem.perBankWrBursts::2 5365 # Per bank write bursts
system.physmem.perBankWrBursts::3 5927 # Per bank write bursts
system.physmem.perBankWrBursts::4 5380 # Per bank write bursts
system.physmem.perBankWrBursts::5 5714 # Per bank write bursts
system.physmem.perBankWrBursts::6 5766 # Per bank write bursts
system.physmem.perBankWrBursts::7 6373 # Per bank write bursts
system.physmem.perBankWrBursts::8 6011 # Per bank write bursts
system.physmem.perBankWrBursts::9 5951 # Per bank write bursts
system.physmem.perBankWrBursts::10 5678 # Per bank write bursts
system.physmem.perBankWrBursts::11 4910 # Per bank write bursts
system.physmem.perBankWrBursts::12 5493 # Per bank write bursts
system.physmem.perBankWrBursts::13 5839 # Per bank write bursts
system.physmem.perBankWrBursts::14 5189 # Per bank write bursts
system.physmem.perBankWrBursts::15 4979 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2816505052000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 1 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 92279 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 90309 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 60465 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 28317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2940 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 476 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2426 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5984 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 3952 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 3780 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 3756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 3603 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 87 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 77 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 33947 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 341.579050 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 192.896082 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 361.051588 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12589 37.08% 37.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 7648 22.53% 59.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3047 8.98% 68.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1722 5.07% 73.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1227 3.61% 77.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 803 2.37% 79.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 549 1.62% 81.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 558 1.64% 82.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5804 17.10% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 33947 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 3440 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.800581 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 525.347088 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 3439 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 3440 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 3440 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 25.865407 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 20.895854 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 25.306431 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 5 0.15% 0.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 3 0.09% 0.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 4 0.12% 0.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 2693 78.28% 78.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 34 0.99% 79.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 21 0.61% 80.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 172 5.00% 85.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 62 1.80% 87.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 30 0.87% 87.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 17 0.49% 88.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 16 0.47% 88.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 84 2.44% 91.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 11 0.32% 91.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 14 0.41% 92.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 10 0.29% 92.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 20 0.58% 92.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.17% 93.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 6 0.17% 93.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 25 0.73% 94.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 46 1.34% 95.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 4 0.12% 95.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 4 0.12% 95.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 9 0.26% 95.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 47 1.37% 97.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.09% 97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 6 0.17% 97.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.06% 97.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 16 0.47% 97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.03% 98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 7 0.20% 98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 2 0.06% 98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 22 0.64% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 3 0.09% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.06% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 6 0.17% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 3 0.09% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.09% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.03% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 3 0.09% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 4 0.12% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.03% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.03% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.06% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.03% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 3 0.09% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223 1 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 1 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 1 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-251 1 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 3440 # Writes before turning the bus around for reads
system.physmem.totQLat 1163516500 # Total ticks spent queuing
system.physmem.totMemAccLat 2892379000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 461030000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12618.66 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 31368.66 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.09 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.02 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.10 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.05 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 6.25 # Average write queue length when enqueuing
system.physmem.readRowHits 76428 # Number of row buffer hits during reads
system.physmem.writeRowHits 70807 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.56 # Row buffer hit rate for writes
system.physmem.avgGap 15425212.92 # Average gap between requests
system.physmem.pageHitRate 81.25 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 134288280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 73012500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 369306600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 291126960 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 68915344410 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1612195386000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1860850713630 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.510917 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2632883157750 # Time in different power states
system.physmem_0.memoryStateTime::REF 91447980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 14405588500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 122351040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 66577500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 349884600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 285444000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 68134185630 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1610493455250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1858324146900 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.557325 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2634053636000 # Time in different power states
system.physmem_1.memoryStateTime::REF 91447980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 13230281250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 5757 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 5757 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 5757 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 5757 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 5757 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.475514 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 87128456868 52.45% 52.45% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 78993152250 47.55% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 166121609118 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 3229 67.67% 67.67% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1543 32.33% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 4772 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5757 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5757 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4772 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4772 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 10529 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 14474153 # DTB read hits
system.cpu0.dtb.read_misses 4865 # DTB read misses
system.cpu0.dtb.write_hits 11054581 # DTB write hits
system.cpu0.dtb.write_misses 892 # DTB write misses
system.cpu0.dtb.flush_tlb 188 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3207 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 943 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 195 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 14479018 # DTB read accesses
system.cpu0.dtb.write_accesses 11055473 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 25528734 # DTB hits
system.cpu0.dtb.misses 5757 # DTB misses
system.cpu0.dtb.accesses 25534491 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 2755 # Table walker walks requested
system.cpu0.itb.walker.walksShort 2755 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 2755 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 2755 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 2755 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.475515 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 87128348368 52.45% 52.45% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 78993260750 47.55% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 166121609118 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 1528 75.53% 75.53% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 495 24.47% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2755 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2755 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 4778 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 67991390 # ITB inst hits
system.cpu0.itb.inst_misses 2755 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 188 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 1966 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 67994145 # ITB inst accesses
system.cpu0.itb.hits 67991390 # DTB hits
system.cpu0.itb.misses 2755 # DTB misses
system.cpu0.itb.accesses 67994145 # DTB accesses
system.cpu0.numCycles 82552372 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 66182532 # Number of instructions committed
system.cpu0.committedOps 80633643 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 70853114 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5470 # Number of float alu accesses
system.cpu0.num_func_calls 7266071 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 8791663 # number of instructions that are conditional controls
system.cpu0.num_int_insts 70853114 # number of integer instructions
system.cpu0.num_fp_insts 5470 # number of float instructions
system.cpu0.num_int_register_reads 131368884 # number of times the integer registers were read
system.cpu0.num_int_register_writes 49289864 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 4246 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 245759484 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 29458192 # number of times the CC registers were written
system.cpu0.num_mem_refs 26200850 # number of memory refs
system.cpu0.num_load_insts 14651277 # Number of load instructions
system.cpu0.num_store_insts 11549573 # Number of store instructions
system.cpu0.num_idle_cycles 77943726.541103 # Number of idle cycles
system.cpu0.num_busy_cycles 4608645.458897 # Number of busy cycles
system.cpu0.not_idle_fraction 0.055827 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.944173 # Percentage of idle cycles
system.cpu0.Branches 16455843 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 55777669 67.99% 67.99% # Class of executed instruction
system.cpu0.op_class::IntMult 58831 0.07% 68.06% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 4520 0.01% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction
system.cpu0.op_class::MemRead 14651277 17.86% 85.92% # Class of executed instruction
system.cpu0.op_class::MemWrite 11549573 14.08% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 82044063 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3055 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 833838 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 46974042 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 834350 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 56.300164 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.894462 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.632625 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.469713 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949013 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032486 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018496 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 198459549 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 198459549 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 13785736 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 4396523 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 8506631 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 26688890 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 10662175 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3165503 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 5162158 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18989836 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190654 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60573 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130462 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 381689 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235825 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80326 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 134935 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 451086 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 237211 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82830 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 139650 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 459691 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 24447911 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 7562026 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 13668789 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 45678726 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 24638565 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 7622599 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 13799251 # number of overall hits
system.cpu0.dcache.overall_hits::total 46060415 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 191504 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 58959 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 314968 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 565431 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 143878 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 35403 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 1532172 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1711453 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54012 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 21177 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65552 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 140741 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4456 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3300 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9701 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 17457 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 16 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 335382 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 94362 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1847140 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2276884 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 389394 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 115539 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1912692 # number of overall misses
system.cpu0.dcache.overall_misses::total 2417625 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 898816250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5241989350 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 6140805600 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1325719411 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70529735198 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 71855454609 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46466000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132057494 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 178523494 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 259504 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 259504 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 2224535661 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 75771724548 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 77996260209 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 2224535661 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 75771724548 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 77996260209 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 13977240 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 4455482 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 8821599 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 27254321 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 10806053 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 3200906 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 6694330 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 20701289 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 244666 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 81750 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 196014 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 522430 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 240281 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83626 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 144636 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 468543 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 237213 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82830 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 139666 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 459709 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 24783293 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 7656388 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 15515929 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 47955610 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 25027959 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 7738138 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 15711943 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 48478040 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013701 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013233 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035704 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.020746 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013315 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011060 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228876 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.082674 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.220758 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.259046 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334425 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269397 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018545 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039461 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.067072 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037258 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000115 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000039 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013533 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012325 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.119048 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.047479 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015558 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014931 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121735 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.049871 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.767550 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16642.926742 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10860.397820 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37446.527441 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46032.518019 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41985.058666 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14080.606061 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13612.771261 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10226.470413 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16219 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14416.888889 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23574.486138 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41021.105356 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 34255.702183 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19253.547815 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39615.225320 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32261.521207 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 372760 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 22765 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 24978 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 525 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.923533 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 43.361905 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 692729 # number of writebacks
system.cpu0.dcache.writebacks::total 692729 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 123 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 154842 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 154965 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1412163 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1412163 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1954 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6831 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8785 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 123 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 1567005 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1567128 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 123 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 1567005 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1567128 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58836 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160126 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 218962 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35403 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 120009 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 155412 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20795 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43908 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 64703 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1346 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2870 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4216 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 16 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 94239 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 280135 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 374374 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 115034 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 324043 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 439077 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 777918000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2124515706 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2902433706 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1248908571 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5424851729 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6673760300 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 265951000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 654196260 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 920147260 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21422750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35664251 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57087001 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 227496 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227496 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2026826571 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7549367435 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9576194006 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2292777571 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8203563695 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10496341266 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019447000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1696986500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2716433500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 779587000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1319132500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2098719500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1799034000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3016119000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4815153000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013205 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018152 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011060 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017927 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007507 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.254373 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224004 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123850 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019843 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008998 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000115 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012309 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018055 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.007807 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014866 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020624 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.009057 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13221.802978 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13267.774790 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13255.421973 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35276.913567 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45203.707464 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42942.374463 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12789.180091 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14899.249795 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14221.091140 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15915.861813 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12426.568293 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.560009 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14218.500000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14218.500000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21507.301340 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26949.033270 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25579.217590 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19931.303536 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25316.281157 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23905.468212 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1797406 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.544833 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 100910374 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1797917 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 56.126269 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10928216250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.581873 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.468426 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.494533 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932777 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041931 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024403 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999111 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 104556280 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 104556280 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 67125667 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 21618827 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 12165880 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 100910374 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 67125667 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 21618827 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 12165880 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 100910374 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 67125667 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 21618827 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 12165880 # number of overall hits
system.cpu0.icache.overall_hits::total 100910374 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 867746 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 249012 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 731202 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1847960 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 867746 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 249012 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 731202 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1847960 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 867746 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 249012 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 731202 # number of overall misses
system.cpu0.icache.overall_misses::total 1847960 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3371834500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10026972776 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13398807276 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 3371834500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 10026972776 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13398807276 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 3371834500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 10026972776 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13398807276 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 67993413 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 21867839 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 12897082 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 102758334 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 67993413 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 21867839 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 12897082 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 102758334 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 67993413 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 21867839 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 12897082 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 102758334 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012762 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011387 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056695 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.017984 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012762 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011387 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056695 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.017984 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012762 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011387 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056695 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.017984 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13540.851445 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.999658 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 7250.593777 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13540.851445 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.999658 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 7250.593777 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13540.851445 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.999658 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 7250.593777 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 6029 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 382 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.782723 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50013 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 50013 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 50013 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 50013 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 50013 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 50013 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 249012 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 681189 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 930201 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 249012 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 681189 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 930201 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 249012 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 681189 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 930201 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2873083500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8182514470 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11055597970 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2873083500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8182514470 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11055597970 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2873083500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8182514470 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11055597970 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009052 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009052 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009052 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11885.171022 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 1854 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 1854 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 620 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1234 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 1854 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 1854 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 1854 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 1496 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 9777.746658 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 7722.280706 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6250.292235 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 511 34.16% 34.16% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 754 50.40% 84.56% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 15.37% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 1496 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1000015000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1000015000 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1000015000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 885 59.16% 59.16% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 611 40.84% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 1496 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1854 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1854 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1496 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1496 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 3350 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 4626652 # DTB read hits
system.cpu1.dtb.read_misses 1593 # DTB read misses
system.cpu1.dtb.write_hits 3288334 # DTB write hits
system.cpu1.dtb.write_misses 261 # DTB write misses
system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1268 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 69 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 4628245 # DTB read accesses
system.cpu1.dtb.write_accesses 3288595 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 7914986 # DTB hits
system.cpu1.dtb.misses 1854 # DTB misses
system.cpu1.dtb.accesses 7916840 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 832 # Table walker walks requested
system.cpu1.itb.walker.walksShort 832 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 221 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 611 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 832 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 832 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 832 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 612 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10456.699346 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 8281.924765 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 6395.528631 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::2048-4095 192 31.37% 31.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-6143 1 0.16% 31.54% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287 290 47.39% 78.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335 12 1.96% 80.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-22527 105 17.16% 98.04% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575 12 1.96% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 612 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 391 63.89% 63.89% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 221 36.11% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 612 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 832 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 832 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 612 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 612 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 1444 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 21867839 # ITB inst hits
system.cpu1.itb.inst_misses 832 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 672 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 21868671 # ITB inst accesses
system.cpu1.itb.hits 21867839 # DTB hits
system.cpu1.itb.misses 832 # DTB misses
system.cpu1.itb.accesses 21868671 # DTB accesses
system.cpu1.numCycles 158011786 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 21167008 # Number of instructions committed
system.cpu1.committedOps 25384727 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 22581810 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1738 # Number of float alu accesses
system.cpu1.num_func_calls 2402385 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2688390 # number of instructions that are conditional controls
system.cpu1.num_int_insts 22581810 # number of integer instructions
system.cpu1.num_fp_insts 1738 # number of float instructions
system.cpu1.num_int_register_reads 41656503 # number of times the integer registers were read
system.cpu1.num_int_register_writes 15851657 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1290 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 92262793 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 9324878 # number of times the CC registers were written
system.cpu1.num_mem_refs 8128633 # number of memory refs
system.cpu1.num_load_insts 4673659 # Number of load instructions
system.cpu1.num_store_insts 3454974 # Number of store instructions
system.cpu1.num_idle_cycles 151523982.353984 # Number of idle cycles
system.cpu1.num_busy_cycles 6487803.646016 # Number of busy cycles
system.cpu1.not_idle_fraction 0.041059 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.958941 # Percentage of idle cycles
system.cpu1.Branches 5241513 # Number of branches fetched
system.cpu1.op_class::No_OpClass 34 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 17951469 68.78% 68.78% # Class of executed instruction
system.cpu1.op_class::IntMult 18860 0.07% 68.85% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 1172 0.00% 68.86% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.86% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.86% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.86% # Class of executed instruction
system.cpu1.op_class::MemRead 4673659 17.91% 86.76% # Class of executed instruction
system.cpu1.op_class::MemWrite 3454974 13.24% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 26100168 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 17449157 # Number of BP lookups
system.cpu2.branchPred.condPredicted 9464735 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 398390 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 10718645 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 8165775 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 76.182904 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4093661 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 20704 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.walker.walks 43517 # Table walker walks requested
system.cpu2.dtb.walker.walksShort 43517 # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13970 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11118 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksSquashedBefore 18429 # Table walks squashed before starting
system.cpu2.dtb.walker.walkWaitTime::samples 25088 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::mean 493.961256 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::stdev 3141.545513 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0-8191 24512 97.70% 97.70% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::8192-16383 373 1.49% 99.19% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::16384-24575 135 0.54% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::24576-32767 33 0.13% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::32768-40959 15 0.06% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::40960-49151 7 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 25088 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 9234 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 11931.507147 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 9422.312939 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 7440.393288 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-8191 2697 29.21% 29.21% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::8192-16383 4034 43.69% 72.89% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2262 24.50% 97.39% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::24576-32767 120 1.30% 98.69% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-40959 50 0.54% 99.23% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::40960-49151 64 0.69% 99.92% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::49152-57343 4 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::73728-81919 2 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 9234 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 52111304876 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::mean 0.433489 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::stdev 0.514696 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0-1 52056176876 99.89% 99.89% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::2-3 40469500 0.08% 99.97% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::4-5 8303000 0.02% 99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::6-7 2155500 0.00% 99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::8-9 1410500 0.00% 99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::10-11 753500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::12-13 454000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::14-15 1056000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::16-17 83500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::18-19 122000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::20-21 61500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::22-23 86000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::24-25 164500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::26-27 4000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::28-29 4500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 52111304876 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 2902 72.88% 72.88% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::1M 1080 27.12% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 3982 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43517 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43517 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3982 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3982 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 47499 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 9677625 # DTB read hits
system.cpu2.dtb.read_misses 37716 # DTB read misses
system.cpu2.dtb.write_hits 7160348 # DTB write hits
system.cpu2.dtb.write_misses 5801 # DTB write misses
system.cpu2.dtb.flush_tlb 182 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 2469 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 945 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 418 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 9715341 # DTB read accesses
system.cpu2.dtb.write_accesses 7166149 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 16837973 # DTB hits
system.cpu2.dtb.misses 43517 # DTB misses
system.cpu2.dtb.accesses 16881490 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.itb.walker.walks 6476 # Table walker walks requested
system.cpu2.itb.walker.walksShort 6476 # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2218 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4151 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting
system.cpu2.itb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::mean 1246.035484 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::stdev 5374.992147 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0-8191 6033 94.72% 94.72% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::8192-16383 153 2.40% 97.13% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::16384-24575 113 1.77% 98.90% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::24576-32767 28 0.44% 99.34% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.30% 99.64% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.13% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::49152-57343 9 0.14% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 1962 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 12125.644750 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 9197.080965 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 8421.034460 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-8191 606 30.89% 30.89% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::8192-16383 818 41.69% 72.58% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::16384-24575 463 23.60% 96.18% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::24576-32767 28 1.43% 97.60% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-40959 29 1.48% 99.08% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::40960-49151 11 0.56% 99.64% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::49152-57343 5 0.25% 99.90% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::57344-65535 1 0.05% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::73728-81919 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 1962 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 4866645120 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::mean 0.377306 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::stdev 0.486503 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 3033838520 62.34% 62.34% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::1 1830102100 37.61% 99.94% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::2 2122000 0.04% 99.99% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::3 461500 0.01% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::4 121000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 4866645120 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 1443 77.79% 77.79% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::1M 412 22.21% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 1855 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6476 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6476 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1855 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1855 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 8331 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 12898498 # ITB inst hits
system.cpu2.itb.inst_misses 6476 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 182 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 1789 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 12904974 # ITB inst accesses
system.cpu2.itb.hits 12898498 # DTB hits
system.cpu2.itb.misses 6476 # DTB misses
system.cpu2.itb.accesses 12904974 # DTB accesses
system.cpu2.numCycles 69896550 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 26772867 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 69167442 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 17449157 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 12259436 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 39647350 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 2075847 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 94572 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 925 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 261 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 361977 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 99094 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 575 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 12897087 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 269205 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 2824 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 68015518 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.222532 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.345771 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 49396866 72.63% 72.63% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 2407853 3.54% 76.17% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 1558370 2.29% 78.46% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 4909650 7.22% 85.68% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 1103212 1.62% 87.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 700919 1.03% 88.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 3889597 5.72% 94.05% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 749830 1.10% 95.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 3299221 4.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 68015518 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.249643 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.989569 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 18660323 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 36954486 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 10395816 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 1074729 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 929937 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 1306815 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 109505 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 59278443 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 354551 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 929937 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 19281301 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 4387069 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 27167714 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 10836297 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 5412952 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 56807794 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2395 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 934627 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 156415 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 3819110 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 58701003 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 260943920 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 63689416 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 4317 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 48649356 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 10051631 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 957722 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 893887 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 6244990 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 10262812 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 7930622 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 1370921 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 1928187 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 54587761 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 670112 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 51973443 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 68390 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 7260181 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 18315253 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 68730 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 68015518 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.466174 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 47556774 69.92% 69.92% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 6833375 10.05% 79.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 5102327 7.50% 87.47% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 4195165 6.17% 93.64% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 1616653 2.38% 96.01% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1064575 1.57% 97.58% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 1125788 1.66% 99.23% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 361184 0.53% 99.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 159677 0.23% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 68015518 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 78584 9.71% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 1 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 374915 46.33% 56.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 355764 43.96% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 110 0.00% 0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 34433275 66.25% 66.25% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 39265 0.08% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 2873 0.01% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 9958899 19.16% 85.49% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 7539012 14.51% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 51973443 # Type of FU issued
system.cpu2.iq.rate 0.743577 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 809264 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.015571 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 172830468 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 62550700 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 50376095 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 9590 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 5049 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 4207 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 52777410 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 5187 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 265138 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 1600472 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1933 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 38461 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 793125 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 131320 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 120276 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 929937 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 3246832 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 971285 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 55360766 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 91934 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 10262812 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 7930622 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 358706 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 34253 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 928134 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 38461 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 182765 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 162631 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 345396 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 51539725 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 9783295 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 390308 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 102893 # number of nop insts executed
system.cpu2.iew.exec_refs 17248466 # number of memory reference insts executed
system.cpu2.iew.exec_branches 9490874 # Number of branches executed
system.cpu2.iew.exec_stores 7465171 # Number of stores executed
system.cpu2.iew.exec_rate 0.737372 # Inst execution rate
system.cpu2.iew.wb_sent 51085657 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 50380302 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 26454346 # num instructions producing a value
system.cpu2.iew.wb_consumers 45953910 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 0.720784 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.575671 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 8107084 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 601382 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 290377 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 66292417 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.712682 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.616986 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 48208105 72.72% 72.72% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 8091600 12.21% 84.93% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 3999207 6.03% 90.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 1724132 2.60% 93.56% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 877027 1.32% 94.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 615427 0.93% 95.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 1259890 1.90% 97.71% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 297840 0.45% 98.16% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 1219189 1.84% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 66292417 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 38883433 # Number of instructions committed
system.cpu2.commit.committedOps 47245385 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 15799837 # Number of memory references committed
system.cpu2.commit.loads 8662340 # Number of loads committed
system.cpu2.commit.membars 225899 # Number of memory barriers committed
system.cpu2.commit.branches 8915887 # Number of branches committed
system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 41357490 # Number of committed integer instructions.
system.cpu2.commit.function_calls 1642928 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 31404754 66.47% 66.47% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 37921 0.08% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.55% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 2873 0.01% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 8662340 18.33% 84.89% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 7137497 15.11% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 47245385 # Class of committed instruction
system.cpu2.commit.bw_lim_events 1219189 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 113003070 # The number of ROB reads
system.cpu2.rob.rob_writes 112431430 # The number of ROB writes
system.cpu2.timesIdled 280451 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1881032 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 5250223632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 38822148 # Number of Instructions Simulated
system.cpu2.committedOps 47184100 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.800430 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.800430 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.555423 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.555423 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 56420474 # number of integer regfile reads
system.cpu2.int_regfile_writes 31939226 # number of integer regfile writes
system.cpu2.fp_regfile_reads 15888 # number of floating regfile reads
system.cpu2.fp_regfile_writes 13694 # number of floating regfile writes
system.cpu2.cc_regfile_reads 182315650 # number of cc regfile reads
system.cpu2.cc_regfile_writes 19227541 # number of cc regfile writes
system.cpu2.misc_regfile_reads 124375401 # number of misc regfile reads
system.cpu2.misc_regfile_writes 481787 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
system.iobus.trans_dist::WriteReq 59019 # Transaction distribution
system.iobus.trans_dist::WriteResp 22795 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 2807000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15727000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 217868633 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 39885000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 22990014 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36442 # number of replacements
system.iocache.tags.tagsinuse 0.993331 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 245002453509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 0.993331 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062083 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062083 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 14419928 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 14419928 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6024842691 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 6024842691 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide 14419928 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14419928 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 14419928 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14419928 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 57221.936508 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166321.849906 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 166321.849906 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 57221.936508 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 57221.936508 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 34568 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 4486 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 7.705751 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 127 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22736 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 22736 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 127 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 127 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 127 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 127 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 7815928 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 7815928 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4842542719 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4842542719 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 7815928 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 7815928 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 7815928 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 7815928 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.503968 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627650 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627650 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.503968 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.503968 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212990.091441 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212990.091441 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 100812 # number of replacements
system.l2c.tags.tagsinuse 65118.584894 # Cycle average of tags in use
system.l2c.tags.total_refs 2893892 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 166052 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 17.427625 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 49801.969845 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939327 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5299.216432 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2852.911552 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969199 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1106.770268 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 948.162110 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 57.070020 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 3510.700878 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 1538.875168 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.759918 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.080860 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.043532 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.016888 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.014468 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000871 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.053569 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.023481 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993631 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65191 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 49 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7961 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53600 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000748 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994736 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 27438611 # Number of tag accesses
system.l2c.tags.data_accesses 27438611 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 5008 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 2568 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 857894 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 243025 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 1381 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 686 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 247021 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 78422 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 27314 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 6601 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 673200 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 202331 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2345451 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 692729 # number of Writeback hits
system.l2c.Writeback_hits::total 692729 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 31 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 80142 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 20956 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 56564 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 157662 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 5008 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 2568 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 857894 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 323167 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 1381 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 686 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 247021 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 99378 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 27314 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 6601 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 673200 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 258895 # number of demand (read+write) hits
system.l2c.demand_hits::total 2503113 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 5008 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 2568 # number of overall hits
system.l2c.overall_hits::cpu0.inst 857894 # number of overall hits
system.l2c.overall_hits::cpu0.data 323167 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 1381 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 686 # number of overall hits
system.l2c.overall_hits::cpu1.inst 247021 # number of overall hits
system.l2c.overall_hits::cpu1.data 99378 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 27314 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 6601 # number of overall hits
system.l2c.overall_hits::cpu2.inst 673200 # number of overall hits
system.l2c.overall_hits::cpu2.data 258895 # number of overall hits
system.l2c.overall_hits::total 2503113 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 9847 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6947 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1990 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 2555 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 94 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 7907 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 4559 # number of ReadReq misses
system.l2c.ReadReq_misses::total 33905 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1226 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 430 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 1061 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2717 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data 4 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 62501 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 14012 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 62367 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 138880 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 9847 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 69448 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1990 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 16567 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 94 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 7907 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 66926 # number of demand (read+write) misses
system.l2c.demand_misses::total 172785 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.inst 9847 # number of overall misses
system.l2c.overall_misses::cpu0.data 69448 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1990 # number of overall misses
system.l2c.overall_misses::cpu1.data 16567 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 94 # number of overall misses
system.l2c.overall_misses::cpu2.inst 7907 # number of overall misses
system.l2c.overall_misses::cpu2.data 66926 # number of overall misses
system.l2c.overall_misses::total 172785 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 145472000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 191058000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7840000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 604236250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 365385246 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1314065996 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 279988 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 302987 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data 46998 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 984500010 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 4647758244 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 5632258254 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 145472000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1175558010 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 7840000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 604236250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 5013143490 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6946324250 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 145472000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1175558010 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 7840000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 604236250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 5013143490 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6946324250 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 5012 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 2569 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 867741 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 249972 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 1382 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 686 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 249011 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 80977 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 27408 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 6601 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 681107 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 206890 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2379356 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 692729 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 692729 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1235 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 435 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 1092 # number of UpgradeReq accesses(hits+misses)
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system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58213.978994 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63863.659370 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62550.140576 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 61856.475401 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60462.060302 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58213.978994 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63863.659370 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62550.140576 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 61856.475401 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 74222 # Transaction distribution
system.membus.trans_dist::ReadResp 74221 # Transaction distribution
system.membus.trans_dist::WriteReq 27571 # Transaction distribution
system.membus.trans_dist::WriteResp 27571 # Transaction distribution
system.membus.trans_dist::Writeback 129099 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4550 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4556 # Transaction distribution
system.membus.trans_dist::ReadExReq 137047 # Transaction distribution
system.membus.trans_dist::ReadExResp 137047 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471572 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 579034 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109015 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109015 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 688049 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16929468 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17092587 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642496 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4642496 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 21735083 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 289 # Total snoops (count)
system.membus.snoop_fanout::samples 341035 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 341035 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 341035 # Request fanout histogram
system.membus.reqLayer0.occupancy 40827000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 469500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 937138500 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 904275509 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 23892986 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 2442249 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2442245 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 692729 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 22736 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296542 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296542 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3613854 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484499 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29280 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87986 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 6215619 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115099320 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97925875 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49208 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154964 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 213229367 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 51973 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3430536 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.102566 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 3394060 98.94% 98.94% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 36476 1.06% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3430536 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2377189197 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 558000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4188720502 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2021336108 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 12001413 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 39606873 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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