sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt

1889 lines
223 KiB
Plaintext
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 51.562170 # Number of seconds simulated
sim_ticks 51562169701000 # Number of ticks simulated
final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 82472 # Simulator instruction rate (inst/s)
host_op_rate 96938 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3850541751 # Simulator tick rate (ticks/s)
host_mem_usage 726532 # Number of bytes of host memory used
host_seconds 13390.89 # Real time elapsed on the host
sim_insts 1104366834 # Number of instructions simulated
sim_ops 1298086167 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory
system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2467786 # Number of read requests accepted
system.physmem.writeReqs 2184211 # Number of write requests accepted
system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue
system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 149005 # Per bank write bursts
system.physmem.perBankRdBursts::1 156339 # Per bank write bursts
system.physmem.perBankRdBursts::2 155955 # Per bank write bursts
system.physmem.perBankRdBursts::3 150628 # Per bank write bursts
system.physmem.perBankRdBursts::4 148084 # Per bank write bursts
system.physmem.perBankRdBursts::5 159303 # Per bank write bursts
system.physmem.perBankRdBursts::6 149188 # Per bank write bursts
system.physmem.perBankRdBursts::7 152515 # Per bank write bursts
system.physmem.perBankRdBursts::8 150862 # Per bank write bursts
system.physmem.perBankRdBursts::9 179370 # Per bank write bursts
system.physmem.perBankRdBursts::10 150320 # Per bank write bursts
system.physmem.perBankRdBursts::11 155893 # Per bank write bursts
system.physmem.perBankRdBursts::12 152080 # Per bank write bursts
system.physmem.perBankRdBursts::13 155961 # Per bank write bursts
system.physmem.perBankRdBursts::14 150556 # Per bank write bursts
system.physmem.perBankRdBursts::15 150970 # Per bank write bursts
system.physmem.perBankWrBursts::0 132106 # Per bank write bursts
system.physmem.perBankWrBursts::1 138501 # Per bank write bursts
system.physmem.perBankWrBursts::2 137398 # Per bank write bursts
system.physmem.perBankWrBursts::3 135602 # Per bank write bursts
system.physmem.perBankWrBursts::4 133392 # Per bank write bursts
system.physmem.perBankWrBursts::5 140433 # Per bank write bursts
system.physmem.perBankWrBursts::6 132940 # Per bank write bursts
system.physmem.perBankWrBursts::7 137025 # Per bank write bursts
system.physmem.perBankWrBursts::8 135656 # Per bank write bursts
system.physmem.perBankWrBursts::9 141181 # Per bank write bursts
system.physmem.perBankWrBursts::10 134433 # Per bank write bursts
system.physmem.perBankWrBursts::11 138339 # Per bank write bursts
system.physmem.perBankWrBursts::12 136301 # Per bank write bursts
system.physmem.perBankWrBursts::13 138853 # Per bank write bursts
system.physmem.perBankWrBursts::14 135122 # Per bank write bursts
system.physmem.perBankWrBursts::15 134659 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 21 # Number of times write queue was full causing retry
system.physmem.totGap 51562168447500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 2446501 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 2181638 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 413 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 181 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 136231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 138984 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 139007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 140497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 136343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 166652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 162914 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 137438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 145049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 131294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 374 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 409 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 389 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 367 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads
system.physmem.totQLat 61876185756 # Total ticks spent queuing
system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
system.physmem.readRowHits 2056722 # Number of row buffer hits during reads
system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes
system.physmem.avgGap 11083878.27 # Average gap between requests
system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.871313 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states
system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.883816 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states
system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu.branchPred.lookups 288825634 # Number of BP lookups
system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups
system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 1430156 # Table walker walks requested
system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 217117628 # DTB read hits
system.cpu.dtb.read_misses 1002788 # DTB read misses
system.cpu.dtb.write_hits 192115888 # DTB write hits
system.cpu.dtb.write_misses 427368 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 218120416 # DTB read accesses
system.cpu.dtb.write_accesses 192543256 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 409233516 # DTB hits
system.cpu.dtb.misses 1430156 # DTB misses
system.cpu.dtb.accesses 410663672 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 177415 # Table walker walks requested
system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 461294711 # ITB inst hits
system.cpu.itb.inst_misses 177415 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 461472126 # ITB inst accesses
system.cpu.itb.hits 461294711 # DTB hits
system.cpu.itb.misses 177415 # DTB misses
system.cpu.itb.accesses 461472126 # DTB accesses
system.cpu.numCycles 2141240199 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed
system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued
system.cpu.iq.rate 0.633727 # Inst issue rate
system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 272684 # number of nop insts executed
system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed
system.cpu.iew.exec_branches 255119365 # Number of branches executed
system.cpu.iew.exec_stores 192124980 # Number of stores executed
system.cpu.iew.exec_rate 0.627523 # Inst execution rate
system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back
system.cpu.iew.wb_producers 573421420 # num instructions producing a value
system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1104366834 # Number of instructions committed
system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 393173853 # Number of memory references committed
system.cpu.commit.loads 204756836 # Number of loads committed
system.cpu.commit.membars 9104821 # Number of memory barriers committed
system.cpu.commit.branches 246834909 # Number of branches committed
system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions.
system.cpu.commit.function_calls 30876862 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction
system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3405665880 # The number of ROB reads
system.cpu.rob.rob_writes 2734432791 # The number of ROB writes
system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 1104366834 # Number of Instructions Simulated
system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads
system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads
system.cpu.int_regfile_writes 940526203 # number of integer regfile writes
system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads
system.cpu.fp_regfile_writes 765828 # number of floating regfile writes
system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads
system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes
system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads
system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes
system.cpu.dcache.tags.replacements 13614186 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1595334423 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1595334423 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 186468319 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 186468319 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 162903680 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 162903680 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 463393 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 463393 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4787397 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4787397 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5271269 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5271269 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 349371999 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 349371999 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 349835392 # number of overall hits
system.cpu.dcache.overall_hits::total 349835392 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 12723000 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 12723000 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 18625078 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 18625078 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2035956 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2035956 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 31348078 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 33384034 # number of overall misses
system.cpu.dcache.overall_misses::total 33384034 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 203343916000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 979374659621 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 979374659621 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 74427778402 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 74427778402 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8800618500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 8800618500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1182718575621 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1182718575621 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 199191319 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 199191319 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 181528758 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 181528758 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2499349 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2499349 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5334732 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5334732 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5271276 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5271276 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 380720077 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 380720077 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 383219426 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 383219426 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063873 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.063873 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102601 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.102601 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.814595 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.814595 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791819 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.791819 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102598 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102598 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.082339 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.082339 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.087115 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087115 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37728.583412 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35427.671072 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 46020939 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2096301 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.953402 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 10299062 # number of writebacks
system.cpu.dcache.writebacks::total 10299062 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5706012 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 5706012 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15543150 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 15543150 # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7171 # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total 7171 # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 263403 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 263403 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 21249162 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 21249162 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 21249162 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 21249162 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7016988 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7016988 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3081928 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3081928 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2029224 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 2029224 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263298 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1263298 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283932 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 283932 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 10098916 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 10098916 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 12128140 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 12128140 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32373018500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32373018500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72874671402 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72874671402 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4076865500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4076865500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 16756542 # number of replacements
system.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses
system.cpu.icache.tags.data_accesses 477553750 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits
system.cpu.icache.overall_hits::total 443237235 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 17559241 # number of overall misses
system.cpu.icache.overall_misses::total 17559241 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 232141013891 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 232141013891 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 232141013891 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 232141013891 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 232141013891 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 460796476 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 460796476 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 460796476 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13220.446937 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13220.446937 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 15959 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1225 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 13.027755 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 801966 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 801966 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 801966 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 801966 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 801966 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 801966 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16757275 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 16757275 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 16757275 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 16757275 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 16757275 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 16757275 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 208567956898 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 208567956898 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 1594412000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036366 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.036366 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.036366 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12446.412492 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12446.412492 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 2345734 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65318.237935 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 55622573 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2409067 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 23.088844 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 15659706000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 35816.547430 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 265.508156 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 348.644093 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6890.433367 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 21997.104889 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.546517 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004051 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005320 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.105140 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.335649 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996677 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63093 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54586 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962723 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 506469360 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 506469360 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1313351 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 329734 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1643085 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 10299062 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 10299062 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 12887 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 12887 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1723701 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1723701 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16658716 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 16658716 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8894179 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 8894179 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 672751 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 672751 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 1313351 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 329734 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 16658716 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 10617880 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 28919681 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 1313351 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 329734 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 16658716 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 10617880 # number of overall hits
system.cpu.l2cache.overall_hits::total 28919681 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10281 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8711 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 18992 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 47777 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 47777 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1312732 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1312732 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 98354 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 98354 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 420801 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 420801 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 590547 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 590547 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 10281 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 8711 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 98354 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1733533 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1850879 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 10281 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 8711 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 98354 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1733533 # number of overall misses
system.cpu.l2cache.overall_misses::total 1850879 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 914040000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 769017500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1683057500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 621639500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 621639500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 120138160000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 120138160000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8298337000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 8298337000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37547469500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 37547469500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62416970000 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 62416970000 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 914040000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 769017500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 8298337000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 157685629500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 167667024000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 914040000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 769017500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 8298337000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 157685629500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 167667024000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1323632 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 338445 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1662077 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 10299062 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 10299062 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 60664 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 60664 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3036433 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3036433 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16757070 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 16757070 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9314980 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 9314980 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263298 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1263298 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1323632 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 338445 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 16757070 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 12351413 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 30770560 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1323632 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 338445 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 16757070 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 12351413 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 30770560 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007767 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.025738 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.011427 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787568 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.787568 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.432327 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.432327 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005869 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005869 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045175 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045175 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.467465 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.467465 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007767 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.025738 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005869 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.140351 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060151 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007767 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.025738 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005869 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.140351 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060151 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88905.748468 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88281.196189 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 88619.287068 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13011.271114 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13011.271114 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91517.659355 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91517.659355 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84372.135348 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84372.135348 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89228.565284 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89228.565284 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 105693.484177 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 105693.484177 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88905.748468 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88281.196189 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84372.135348 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90962.000435 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 90587.782346 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88905.748468 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88281.196189 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84372.135348 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90962.000435 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 90587.782346 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2075008 # number of writebacks
system.cpu.l2cache.writebacks::total 2075008 # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10281 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8711 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 18992 # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1261 # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 47777 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 47777 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1312732 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1312732 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 98354 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 98354 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 420779 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 420779 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 590547 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 590547 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10281 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8711 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 98354 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1733511 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1850857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10281 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8711 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 98354 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1733511 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1850857 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54987 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88690 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 811230000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 681907500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1493137500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 993052500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 993052500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 161500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 161500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107010840000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107010840000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7314797000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7314797000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33338388000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33338388000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 56511500000 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 56511500000 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 811230000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 681907500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7314797000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140349228000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 149157162500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 811230000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 681907500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7314797000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140349228000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 149157162500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1328224500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407939500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6736164000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5316157000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5316157000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1328224500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10724096500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12052321000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011427 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787568 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787568 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060150 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060150 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 3104722 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 40298 # Transaction distribution
system.iobus.trans_dist::ReadResp 40298 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115458 # number of replacements
system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
system.iocache.tags.data_accesses 1039650 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8813 # number of overall misses
system.iocache.overall_misses::total 8853 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 54987 # Transaction distribution
system.membus.trans_dist::ReadResp 601962 # Transaction distribution
system.membus.trans_dist::WriteReq 33703 # Transaction distribution
system.membus.trans_dist::WriteResp 33703 # Transaction distribution
system.membus.trans_dist::Writeback 2181638 # Transaction distribution
system.membus.trans_dist::CleanEvict 277040 # Transaction distribution
system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution
system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution
system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2989 # Total snoops (count)
system.membus.snoop_fanout::samples 5154600 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 5154600 # Request fanout histogram
system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink