3907 lines
465 KiB
Text
3907 lines
465 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 47.309815 # Number of seconds simulated
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sim_ticks 47309815475000 # Number of ticks simulated
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final_tick 47309815475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 80227 # Simulator instruction rate (inst/s)
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host_op_rate 94350 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4125416978 # Simulator tick rate (ticks/s)
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host_mem_usage 770696 # Number of bytes of host memory used
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host_seconds 11467.89 # Real time elapsed on the host
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sim_insts 920033396 # Number of instructions simulated
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sim_ops 1081995375 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 174848 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 152512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 4545760 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 43325128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.l2cache.prefetcher 19040640 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 136192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 127232 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 2550688 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 17518992 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.l2cache.prefetcher 15564544 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 439744 # Number of bytes read from this memory
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system.physmem.bytes_read::total 103576280 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 4545760 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 2550688 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 7096448 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 86607680 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
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system.physmem.bytes_written::total 86628264 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 2732 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2383 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 86980 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 676968 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.l2cache.prefetcher 297510 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 2128 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 1988 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 39898 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 273747 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.l2cache.prefetcher 243196 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6871 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1634401 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1353245 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1355819 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 3696 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 3224 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 96085 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 915775 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.l2cache.prefetcher 402467 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 2879 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 2689 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 53915 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 370304 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.l2cache.prefetcher 328992 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 9295 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2189319 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 96085 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 53915 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 149999 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1830649 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1831084 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1830649 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 3696 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 3224 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 96085 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 916210 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.l2cache.prefetcher 402467 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 2879 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 2689 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 53915 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 370304 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.l2cache.prefetcher 328992 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 9295 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4020403 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1634401 # Number of read requests accepted
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system.physmem.writeReqs 1355819 # Number of write requests accepted
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system.physmem.readBursts 1634401 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1355819 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 104570688 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue
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system.physmem.bytesWritten 86627008 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 103576280 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 86628264 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 224542 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 101664 # Per bank write bursts
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system.physmem.perBankRdBursts::1 108898 # Per bank write bursts
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system.physmem.perBankRdBursts::2 93497 # Per bank write bursts
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system.physmem.perBankRdBursts::3 100406 # Per bank write bursts
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system.physmem.perBankRdBursts::4 99202 # Per bank write bursts
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system.physmem.perBankRdBursts::5 111502 # Per bank write bursts
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system.physmem.perBankRdBursts::6 102695 # Per bank write bursts
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system.physmem.perBankRdBursts::7 105017 # Per bank write bursts
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system.physmem.perBankRdBursts::8 95660 # Per bank write bursts
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system.physmem.perBankRdBursts::9 119055 # Per bank write bursts
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system.physmem.perBankRdBursts::10 95976 # Per bank write bursts
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system.physmem.perBankRdBursts::11 99461 # Per bank write bursts
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system.physmem.perBankRdBursts::12 97685 # Per bank write bursts
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system.physmem.perBankRdBursts::13 98791 # Per bank write bursts
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system.physmem.perBankRdBursts::14 102404 # Per bank write bursts
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system.physmem.perBankRdBursts::15 102004 # Per bank write bursts
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system.physmem.perBankWrBursts::0 83138 # Per bank write bursts
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system.physmem.perBankWrBursts::1 88505 # Per bank write bursts
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system.physmem.perBankWrBursts::2 79517 # Per bank write bursts
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system.physmem.perBankWrBursts::3 83751 # Per bank write bursts
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system.physmem.perBankWrBursts::4 82730 # Per bank write bursts
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system.physmem.perBankWrBursts::5 91993 # Per bank write bursts
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system.physmem.perBankWrBursts::6 85763 # Per bank write bursts
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system.physmem.perBankWrBursts::7 87476 # Per bank write bursts
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system.physmem.perBankWrBursts::8 80354 # Per bank write bursts
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system.physmem.perBankWrBursts::9 84626 # Per bank write bursts
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system.physmem.perBankWrBursts::10 82451 # Per bank write bursts
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system.physmem.perBankWrBursts::11 83951 # Per bank write bursts
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system.physmem.perBankWrBursts::12 82076 # Per bank write bursts
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system.physmem.perBankWrBursts::13 85332 # Per bank write bursts
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system.physmem.perBankWrBursts::14 85178 # Per bank write bursts
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system.physmem.perBankWrBursts::15 86706 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 54 # Number of times write queue was full causing retry
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system.physmem.totGap 47309813973500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 25 # Read request sizes (log2)
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system.physmem.readPktSize::4 21333 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1613043 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 2 # Write request sizes (log2)
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system.physmem.writePktSize::3 2572 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1353245 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 578892 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 412924 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 179105 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 178845 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 107013 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 63608 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 33748 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 30706 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 27701 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 8546 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 4578 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 2741 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1308 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 574 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 473 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 388 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 19221 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 22339 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35019 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 41881 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 50025 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 59082 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 67725 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 77253 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 82334 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 88348 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::25 89969 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 94025 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 94875 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 99373 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 112446 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 104983 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 99994 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 89665 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::33 6823 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 3907 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 1575 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 1140 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 893 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 774 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::40 745 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 621 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 501 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 396 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::46 376 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 272 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 303 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 294 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 305 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 202 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 161 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 136 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 146 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1028414 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::mean 185.914855 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 114.442896 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 243.413322 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 618503 60.14% 60.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 202037 19.65% 79.79% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-383 65034 6.32% 86.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 35244 3.43% 89.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 24806 2.41% 91.95% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::640-767 13355 1.30% 93.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 14362 1.40% 94.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 8867 0.86% 95.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 46206 4.49% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1028414 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 77347 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 21.124284 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 260.957500 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-4095 77345 100.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 77347 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 77347 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 17.499670 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 17.056595 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 6.288618 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 72278 93.45% 93.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 2489 3.22% 96.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 567 0.73% 97.40% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 275 0.36% 97.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 300 0.39% 98.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 491 0.63% 98.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 126 0.16% 98.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 49 0.06% 99.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 40 0.05% 99.05% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 44 0.06% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 35 0.05% 99.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 27 0.03% 99.19% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 405 0.52% 99.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 43 0.06% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 50 0.06% 99.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 52 0.07% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 16 0.02% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 23 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 8 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 5 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 77347 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 84737173288 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 115373117038 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 8169585000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 51861.37 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 70611.37 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.70 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 1319893 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 639153 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 80.78 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 47.22 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 15821516.13 # Average gap between requests
|
|
system.physmem.pageHitRate 65.57 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 3982161960 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 2172806625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 6418448400 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 4425017040 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 1165891095180 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 27363173363250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 31636109560215 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.700864 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 45520771842112 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1579778460000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 209258446888 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 3792625200 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 2069388750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 6326026200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 4345967520 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 1161508413915 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 27367017820500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 31635106909845 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.679671 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 45527169156111 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1579778460000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 202865647889 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
|
|
system.cpu0.branchPred.lookups 147707110 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 98263896 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 7114286 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 103765470 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 67713845 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 65.256626 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 20037326 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 200169 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.walker.walks 575296 # Table walker walks requested
|
|
system.cpu0.dtb.walker.walksLong 575296 # Table walker walks initiated with long descriptors
|
|
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12884 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88904 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.dtb.walker.walksSquashedBefore 257665 # Table walks squashed before starting
|
|
system.cpu0.dtb.walker.walkWaitTime::samples 317631 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::mean 2022.074357 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::stdev 12176.572384 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::0-65535 315561 99.35% 99.35% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1443 0.45% 99.80% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::131072-196607 466 0.15% 99.95% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::196608-262143 74 0.02% 99.97% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::262144-327679 64 0.02% 99.99% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.01% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::total 317631 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::samples 284896 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::mean 18154.968831 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::gmean 15325.984047 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::stdev 16062.585690 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::0-32767 269179 94.48% 94.48% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 12793 4.49% 98.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1124 0.39% 99.37% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::98304-131071 999 0.35% 99.72% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 121 0.04% 99.76% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 154 0.05% 99.82% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::196608-229375 275 0.10% 99.91% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::229376-262143 60 0.02% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::262144-294911 49 0.02% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 59 0.02% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::327680-360447 25 0.01% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::360448-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::393216-425983 18 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::491520-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::total 284896 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walksPending::samples 550505269948 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::mean 0.606717 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::stdev 0.533946 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::0-1 549425097448 99.80% 99.80% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::2-3 576911000 0.10% 99.91% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::4-5 232215500 0.04% 99.95% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::6-7 109337500 0.02% 99.97% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::8-9 81684000 0.01% 99.99% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::10-11 43624500 0.01% 99.99% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::12-13 15920500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::14-15 20013500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::16-17 440500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::18-19 25500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::total 550505269948 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walkPageSizes::4K 88905 87.34% 87.34% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::2M 12884 12.66% 100.00% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::total 101789 # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 575296 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 575296 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101789 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101789 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin::total 677085 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 107498760 # DTB read hits
|
|
system.cpu0.dtb.read_misses 398450 # DTB read misses
|
|
system.cpu0.dtb.write_hits 89911233 # DTB write hits
|
|
system.cpu0.dtb.write_misses 176846 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 36343 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 6513 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 39209 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 107897210 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 90088079 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 197409993 # DTB hits
|
|
system.cpu0.dtb.misses 575296 # DTB misses
|
|
system.cpu0.dtb.accesses 197985289 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.walks 88373 # Table walker walks requested
|
|
system.cpu0.itb.walker.walksLong 88373 # Table walker walks initiated with long descriptors
|
|
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1010 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63733 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.itb.walker.walksSquashedBefore 10354 # Table walks squashed before starting
|
|
system.cpu0.itb.walker.walkWaitTime::samples 78019 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::mean 1154.635409 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::stdev 8302.318133 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0-32767 77325 99.11% 99.11% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::32768-65535 373 0.48% 99.59% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::65536-98303 149 0.19% 99.78% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::98304-131071 144 0.18% 99.96% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 78019 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::samples 75097 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::mean 22974.939079 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::gmean 20231.234781 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::stdev 18518.097642 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::0-32767 68416 91.10% 91.10% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::32768-65535 5120 6.82% 97.92% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::65536-98303 490 0.65% 98.57% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::98304-131071 809 1.08% 99.65% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::131072-163839 63 0.08% 99.74% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::163840-196607 55 0.07% 99.81% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::196608-229375 56 0.07% 99.88% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::229376-262143 27 0.04% 99.92% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::262144-294911 16 0.02% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::294912-327679 17 0.02% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::360448-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::total 75097 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walksPending::samples 413042823976 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::mean 0.838558 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::stdev 0.368059 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::0 66699023100 16.15% 16.15% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::1 346328877376 83.85% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::2 13315500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::3 1543000 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::4 65000 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 413042823976 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 63733 98.44% 98.44% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::2M 1010 1.56% 100.00% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::total 64743 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88373 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88373 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64743 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64743 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 153116 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 231997623 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 88373 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 26272 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 223051 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 232085996 # ITB inst accesses
|
|
system.cpu0.itb.hits 231997623 # DTB hits
|
|
system.cpu0.itb.misses 88373 # DTB misses
|
|
system.cpu0.itb.accesses 232085996 # DTB accesses
|
|
system.cpu0.numCycles 807086065 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 93861008 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 652896475 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 147707110 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 87751171 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 672171434 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 15342460 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 1905506 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 292447 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 6425780 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 696882 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 817665 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 231773404 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 1782410 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 29765 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 783841952 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.977378 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 1.220143 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 417241550 53.23% 53.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 142387565 18.17% 71.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 48916006 6.24% 77.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 175296831 22.36% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 783841952 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.183013 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.808955 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 111750908 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 381172853 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 246402586 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 39053255 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 5462350 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 21288781 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 2252861 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 678905918 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 24756446 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 5462350 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 148938841 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 55630896 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 250198036 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 247704695 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 75907134 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 660737654 # Number of instructions processed by rename
|
|
system.cpu0.rename.SquashedInsts 6369939 # Number of squashed instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 10029778 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 264844 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 301380 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 39545548 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 629064095 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 1015658028 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 780465434 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 875541 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 567964584 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 61099508 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 16110257 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 14023115 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 79266160 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 107669777 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 93504359 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 9663954 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 8219387 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 637670623 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 16186083 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 641968825 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 2865871 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 57572234 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 37073972 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 286236 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 783841952 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.819003 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.071442 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 436124999 55.64% 55.64% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 142425457 18.17% 73.81% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 124936152 15.94% 89.75% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 71756087 9.15% 98.90% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 8593482 1.10% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 5775 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 783841952 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 67185359 45.52% 45.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 54880 0.04% 45.56% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 27644 0.02% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 23 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.58% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 37910313 25.69% 71.26% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 42413379 28.74% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 438393066 68.29% 68.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 1458143 0.23% 68.52% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 76119 0.01% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 8 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 85008 0.01% 68.54% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 110671978 17.24% 85.78% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 91284446 14.22% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 641968825 # Type of FU issued
|
|
system.cpu0.iq.rate 0.795416 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 147591598 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.229905 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 2216794106 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 710999195 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 623995458 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 1442965 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 583548 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 537913 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 788669354 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 891059 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 2946784 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 13030035 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 154978 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 6224286 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 2912970 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 4614756 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 5462350 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 6648440 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 5673367 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 653983600 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 107669777 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 93504359 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 13738155 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 65760 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 5541873 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 154978 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 2183890 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 3035421 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 5219311 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 633716914 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 107489609 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 7688831 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 126894 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 197402015 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 119462239 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 89912406 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.785191 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 625355277 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 624533371 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 303033924 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 497197749 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.773813 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.609484 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 50242588 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 15899847 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 4905406 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 774311548 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.770083 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.572660 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 515220918 66.54% 66.54% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 132191074 17.07% 83.61% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 58451829 7.55% 91.16% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 19702970 2.54% 93.70% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 14118724 1.82% 95.53% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 9514083 1.23% 96.76% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 6460440 0.83% 97.59% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 3939203 0.51% 98.10% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 14712307 1.90% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 774311548 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 507069048 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 596284470 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 181919815 # Number of memory references committed
|
|
system.cpu0.commit.loads 94639742 # Number of loads committed
|
|
system.cpu0.commit.membars 4012038 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 113466884 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 524978 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 547272509 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 14945710 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 413008446 69.26% 69.26% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 1219700 0.20% 69.47% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 60724 0.01% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 75743 0.01% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 94639742 15.87% 85.36% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 87280073 14.64% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 596284470 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 14712307 # number cycles where commit BW limit reached
|
|
system.cpu0.rob.rob_reads 1401646047 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 1302545204 # The number of ROB writes
|
|
system.cpu0.timesIdled 1046717 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 23244113 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 93812546108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 507069048 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 596284470 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 1.591669 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 1.591669 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.628271 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.628271 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 748239233 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 444460602 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 860614 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 470540 # number of floating regfile writes
|
|
system.cpu0.cc_regfile_reads 137535879 # number of cc regfile reads
|
|
system.cpu0.cc_regfile_writes 138377705 # number of cc regfile writes
|
|
system.cpu0.misc_regfile_reads 1393834331 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 16112974 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.replacements 6187008 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 505.050028 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 169602823 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 6187519 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 27.410473 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 1887138000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.050028 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986426 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.986426 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 376921548 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 376921548 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 87937173 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 87937173 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 76339825 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 76339825 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228046 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 228046 # number of SoftPFReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 267132 # number of WriteLineReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::total 267132 # number of WriteLineReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1986809 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 1986809 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2024617 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 2024617 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 164276998 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 164276998 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 164505044 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 164505044 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 6895567 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 6895567 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 7624089 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 7624089 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 725854 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 725854 # number of SoftPFReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 804065 # number of WriteLineReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::total 804065 # number of WriteLineReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 277240 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 277240 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200055 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 200055 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 14519656 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 14519656 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 15245510 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 15245510 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102037717000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 102037717000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 136358862160 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 136358862160 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 72398693034 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::total 72398693034 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4092900000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4092900000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4230014500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 4230014500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5283500 # number of StoreCondFailReq miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5283500 # number of StoreCondFailReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 238396579160 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 238396579160 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 238396579160 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 238396579160 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 94832740 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 94832740 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 83963914 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 83963914 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 953900 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 953900 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1071197 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::total 1071197 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2264049 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 2264049 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2224672 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 2224672 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 178796654 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 178796654 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 179750554 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 179750554 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.072713 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.072713 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.090802 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.090802 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760933 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760933 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.750623 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.750623 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122453 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122453 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089926 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089926 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081208 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.081208 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084815 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.084815 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14797.581838 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14797.581838 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17885.266313 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17885.266313 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90040.846243 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90040.846243 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14763.021209 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14763.021209 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21144.257829 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21144.257829 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16418.886175 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 16418.886175 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15637.166560 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 15637.166560 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 22487796 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 20190626 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 731543 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 741822 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.740224 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 27.217616 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 4210788 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 4210788 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3513002 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 3513002 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6114706 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 6114706 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4602 # number of WriteLineReq MSHR hits
|
|
system.cpu0.dcache.WriteLineReq_mshr_hits::total 4602 # number of WriteLineReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 143782 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 143782 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 9627708 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 9627708 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 9627708 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 9627708 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3382565 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 3382565 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1509383 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 1509383 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 718663 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 718663 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 799463 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::total 799463 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 133458 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 133458 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200041 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 200041 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4891948 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 4891948 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5610611 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 5610611 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32342 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64165 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48415097500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48415097500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29340240291 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29340240291 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16426692500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16426692500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 71393732534 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 71393732534 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1844525500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1844525500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4030091500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4030091500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5165500 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5165500 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77755337791 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 77755337791 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94182030291 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 94182030291 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5817539000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5817539000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5518707000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5518707000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11336246000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11336246000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035669 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035669 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017977 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017977 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753394 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.753394 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746327 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746327 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058947 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058947 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089919 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089919 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027360 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027360 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031213 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031213 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14313.131455 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14313.131455 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19438.565487 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19438.565487 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.295422 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.295422 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89302.109709 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89302.109709 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.018598 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.018598 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20146.327503 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20146.327503 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15894.555255 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15894.555255 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16786.412441 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16786.412441 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179875.672500 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179875.672500 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173418.816579 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173418.816579 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176673.357750 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176673.357750 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 6407339 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.955601 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 224970066 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 6407851 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 35.108505 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 17322639000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955601 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 330 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 469899085 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 469899085 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 224970066 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 224970066 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 224970066 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 224970066 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 224970066 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 224970066 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 6775541 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 6775541 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 6775541 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 6775541 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 6775541 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 6775541 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71079582898 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 71079582898 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 71079582898 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 71079582898 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 71079582898 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 71079582898 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 231745607 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 231745607 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 231745607 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 231745607 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 231745607 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 231745607 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029237 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.029237 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029237 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.029237 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029237 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.029237 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10490.613650 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 10490.613650 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 10490.613650 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 10490.613650 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 10215206 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 732 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 767906 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.302678 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 367670 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 367670 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 367670 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 367670 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 367670 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 367670 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6407871 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 6407871 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6407871 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 6407871 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6407871 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 6407871 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64388034562 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 64388034562 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64388034562 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 64388034562 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64388034562 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 64388034562 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027650 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.027650 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.027650 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10048.272595 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.l2cache.prefetcher.num_hwpf_issued 8228747 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.pfIdentified 8235731 # number of prefetch candidates identified
|
|
system.cpu0.l2cache.prefetcher.pfBufferHit 6331 # number of redundant prefetches already in prefetch queue
|
|
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu0.l2cache.prefetcher.pfSpanPage 1065389 # number of prefetches not generated due to page crossing
|
|
system.cpu0.l2cache.tags.replacements 2775717 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 16223.891094 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 21402394 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 2791423 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 7.667198 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 16000650500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 7115.603862 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.900810 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 84.351377 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4177.499611 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3867.898858 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 899.636576 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.434302 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004816 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005148 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.254974 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.236078 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054909 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.990228 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1370 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14231 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 95 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 230 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 633 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 777 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4691 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4874 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3670 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083618 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.868591 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 429969971 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 429969971 # Number of data accesses
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 556706 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 187543 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 744249 # number of ReadReq hits
|
|
system.cpu0.l2cache.Writeback_hits::writebacks 4210780 # number of Writeback hits
|
|
system.cpu0.l2cache.Writeback_hits::total 4210780 # number of Writeback hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 112692 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::total 112692 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36481 # number of SCUpgradeReq hits
|
|
system.cpu0.l2cache.SCUpgradeReq_hits::total 36481 # number of SCUpgradeReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 982818 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 982818 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5746953 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::total 5746953 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3150457 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::total 3150457 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 210597 # number of InvalidateReq hits
|
|
system.cpu0.l2cache.InvalidateReq_hits::total 210597 # number of InvalidateReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 556706 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 187543 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 5746953 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 4133275 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 10624477 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 556706 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 187543 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 5746953 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 4133275 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 10624477 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12834 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9490 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 22324 # number of ReadReq misses
|
|
system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
|
|
system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137568 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 137568 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 163550 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 163550 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 289201 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 289201 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 660894 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::total 660894 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1080002 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::total 1080002 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 587441 # number of InvalidateReq misses
|
|
system.cpu0.l2cache.InvalidateReq_misses::total 587441 # number of InvalidateReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12834 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9490 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 660894 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 1369203 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 2052421 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12834 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9490 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 660894 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 1369203 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 2052421 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 512484500 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 411800500 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::total 924285000 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2995269498 # number of UpgradeReq miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_miss_latency::total 2995269498 # number of UpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3391228500 # number of SCUpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3391228500 # number of SCUpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4985998 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4985998 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15723716499 # number of ReadExReq miss cycles
|
|
system.cpu0.l2cache.ReadExReq_miss_latency::total 15723716499 # number of ReadExReq miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20507752998 # number of ReadCleanReq miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20507752998 # number of ReadCleanReq miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39428872479 # number of ReadSharedReq miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39428872479 # number of ReadSharedReq miss cycles
|
|
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67940497999 # number of InvalidateReq miss cycles
|
|
system.cpu0.l2cache.InvalidateReq_miss_latency::total 67940497999 # number of InvalidateReq miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 512484500 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 411800500 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20507752998 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.data 55152588978 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::total 76584626976 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 512484500 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 411800500 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20507752998 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.data 55152588978 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::total 76584626976 # number of overall miss cycles
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 569540 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 197033 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 766573 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::writebacks 4210782 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::total 4210782 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 250260 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 250260 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200031 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 200031 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1272019 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 1272019 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6407847 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::total 6407847 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4230459 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::total 4230459 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 798038 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu0.l2cache.InvalidateReq_accesses::total 798038 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 569540 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 197033 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 6407847 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 5502478 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 12676898 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 569540 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 197033 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 6407847 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 5502478 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 12676898 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048165 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.029122 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
|
|
system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.549700 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.549700 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.817623 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.817623 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.227356 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.227356 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.103138 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.103138 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255292 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255292 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.736107 # miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.736107 # miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048165 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.103138 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.248834 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.161902 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048165 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.103138 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.248834 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.161902 # miss rate for overall accesses
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 43393.097998 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41403.198352 # average ReadReq miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21773.010424 # average UpgradeReq miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21773.010424 # average UpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20735.117701 # average SCUpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20735.117701 # average SCUpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 498599.800000 # average SCUpgradeFailReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498599.800000 # average SCUpgradeFailReq miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54369.509438 # average ReadExReq miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54369.509438 # average ReadExReq miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31030.321047 # average ReadCleanReq miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31030.321047 # average ReadCleanReq miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36508.147651 # average ReadSharedReq miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36508.147651 # average ReadSharedReq miss latency
|
|
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 115655.015566 # average InvalidateReq miss latency
|
|
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 115655.015566 # average InvalidateReq miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 43393.097998 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31030.321047 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40280.797645 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::total 37314.287359 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 43393.097998 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31030.321047 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40280.797645 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::total 37314.287359 # average overall miss latency
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 1981 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 152.384615 # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.l2cache.writebacks::writebacks 1508833 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 1508833 # number of writebacks
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 7 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 199 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_hits::total 206 # number of ReadReq MSHR hits
|
|
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 18287 # number of ReadExReq MSHR hits
|
|
system.cpu0.l2cache.ReadExReq_mshr_hits::total 18287 # number of ReadExReq MSHR hits
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5427 # number of ReadSharedReq MSHR hits
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5427 # number of ReadSharedReq MSHR hits
|
|
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits
|
|
system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 7 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 199 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 23714 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::total 23929 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 7 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 199 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 23714 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::total 23929 # number of overall MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12827 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9291 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::total 22118 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
|
|
system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
|
|
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 112445 # number of CleanEvict MSHR misses
|
|
system.cpu0.l2cache.CleanEvict_mshr_misses::total 112445 # number of CleanEvict MSHR misses
|
|
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 792314 # number of HardPFReq MSHR misses
|
|
system.cpu0.l2cache.HardPFReq_mshr_misses::total 792314 # number of HardPFReq MSHR misses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 137568 # number of UpgradeReq MSHR misses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 137568 # number of UpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 163550 # number of SCUpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 163550 # number of SCUpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 270914 # number of ReadExReq MSHR misses
|
|
system.cpu0.l2cache.ReadExReq_mshr_misses::total 270914 # number of ReadExReq MSHR misses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 660885 # number of ReadCleanReq MSHR misses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 660885 # number of ReadCleanReq MSHR misses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074575 # number of ReadSharedReq MSHR misses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074575 # number of ReadSharedReq MSHR misses
|
|
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 587435 # number of InvalidateReq MSHR misses
|
|
system.cpu0.l2cache.InvalidateReq_mshr_misses::total 587435 # number of InvalidateReq MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12827 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9291 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 660885 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1345489 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::total 2028492 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12827 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9291 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 660885 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1345489 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 792314 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::total 2820806 # number of overall MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53636 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 85459 # number of overall MSHR uncacheable misses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 348114500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 783506000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 46187185788 # number of HardPFReq MSHR miss cycles
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 46187185788 # number of HardPFReq MSHR miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2827746492 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2827746492 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2511676494 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2511676494 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4277998 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4277998 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11675388499 # number of ReadExReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11675388499 # number of ReadExReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16542258498 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16542258498 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32603545979 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32603545979 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64414833499 # number of InvalidateReq MSHR miss cycles
|
|
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64414833499 # number of InvalidateReq MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 348114500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16542258498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44278934478 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::total 61604698976 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 348114500 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16542258498 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44278934478 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 46187185788 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::total 107791884764 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5558674000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7262714500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5274604967 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5274604967 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10833278967 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12537319467 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028853 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
|
|
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
|
|
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.549700 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.549700 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817623 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817623 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212980 # mshr miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212980 # mshr miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.103137 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254009 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254009 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.736099 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.736099 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.160015 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.222515 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35423.908129 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average HardPFReq mshr miss latency
|
|
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58294.042246 # average HardPFReq mshr miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20555.263521 # average UpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20555.263521 # average UpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15357.239340 # average SCUpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15357.239340 # average SCUpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 427799.800000 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 427799.800000 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43096.290701 # average ReadExReq mshr miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43096.290701 # average ReadExReq mshr miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average ReadCleanReq mshr miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25030.464450 # average ReadCleanReq mshr miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30340.875210 # average ReadSharedReq mshr miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30340.875210 # average ReadSharedReq mshr miss latency
|
|
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 109654.401762 # average InvalidateReq mshr miss latency
|
|
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 109654.401762 # average InvalidateReq mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30369.702703 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38213.150697 # average overall mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171871.683879 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 135407.459542 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165748.199950 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165748.199950 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168834.706881 # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 146705.665489 # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 972246 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 11719640 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 31823 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::Writeback 8100286 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::CleanEvict 11177309 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::HardPFReq 1018919 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 495790 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 366670 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 532232 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 139 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 1670081 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 1283370 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6407871 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6502663 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::InvalidateReq 904766 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::InvalidateResp 798038 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19264194 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20025393 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428101 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1250579 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 40968267 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 410442912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629983858 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1576264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4556320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 1046559354 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 11261603 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 37657626 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 1.313855 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.464058 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 25838573 68.61% 68.61% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 11819053 31.39% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 37657626 # Request fanout histogram
|
|
system.cpu0.toL2Bus.reqLayer0.occupancy 17602075916 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.snoopLayer0.occupancy 231593980 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer0.occupancy 9637654372 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer1.occupancy 8931019988 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer2.occupancy 231432265 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer3.occupancy 681669728 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.branchPred.lookups 121094303 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 80706133 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 6142160 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 84960891 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 56341743 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 66.314915 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 16429988 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 173246 # Number of incorrect RAS predictions.
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 582230 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksLong 582230 # Table walker walks initiated with long descriptors
|
|
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14388 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94420 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.dtb.walker.walksSquashedBefore 278308 # Table walks squashed before starting
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 303922 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::mean 1994.445943 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::stdev 12173.491739 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0-32767 299685 98.61% 98.61% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::32768-65535 2211 0.73% 99.33% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::65536-98303 696 0.23% 99.56% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::98304-131071 740 0.24% 99.81% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::131072-163839 294 0.10% 99.90% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::163840-196607 141 0.05% 99.95% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::196608-229375 47 0.02% 99.96% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::229376-262143 22 0.01% 99.97% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::262144-294911 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::294912-327679 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::327680-360447 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::360448-393215 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::491520-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 303922 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::samples 314895 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::mean 18136.229537 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::gmean 15585.359240 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::stdev 14753.917468 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::0-65535 312363 99.20% 99.20% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1838 0.58% 99.78% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 299 0.09% 99.87% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 215 0.07% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 97 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::total 314895 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walksPending::samples 417361955272 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::mean 0.556480 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::stdev 0.556703 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0-1 416192825272 99.72% 99.72% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::2-3 674141500 0.16% 99.88% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::4-5 223425500 0.05% 99.93% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::6-7 105228000 0.03% 99.96% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::8-9 86739500 0.02% 99.98% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::10-11 43806500 0.01% 99.99% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::12-13 16133000 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::14-15 19234500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::16-17 421500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total 417361955272 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 94420 86.78% 86.78% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::2M 14388 13.22% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 108808 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 582230 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 582230 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108808 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108808 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 691038 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 89807249 # DTB read hits
|
|
system.cpu1.dtb.read_misses 419450 # DTB read misses
|
|
system.cpu1.dtb.write_hits 72180592 # DTB write hits
|
|
system.cpu1.dtb.write_misses 162780 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 41875 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 370 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 6410 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 41502 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 90226699 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 72343372 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 161987841 # DTB hits
|
|
system.cpu1.dtb.misses 582230 # DTB misses
|
|
system.cpu1.dtb.accesses 162570071 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 81350 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksLong 81350 # Table walker walks initiated with long descriptors
|
|
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 844 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59039 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.itb.walker.walksSquashedBefore 9413 # Table walks squashed before starting
|
|
system.cpu1.itb.walker.walkWaitTime::samples 71937 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::mean 1124.310160 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::stdev 8422.739912 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0-65535 71675 99.64% 99.64% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::65536-131071 232 0.32% 99.96% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::131072-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::196608-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 71937 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::samples 69296 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::mean 22634.596514 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::gmean 19851.891028 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::stdev 18070.710028 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::0-65535 67837 97.89% 97.89% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::65536-131071 1226 1.77% 99.66% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::131072-196607 116 0.17% 99.83% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.11% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::total 69296 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walksPending::samples 391589144496 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::mean 0.846934 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::stdev 0.360225 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 59961618480 15.31% 15.31% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::1 331606536516 84.68% 99.99% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::2 19274500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::3 1690500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::4 24500 0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total 391589144496 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 59039 98.59% 98.59% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::2M 844 1.41% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 59883 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81350 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81350 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59883 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59883 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 141233 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 191639831 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 81350 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 29949 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 209776 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 191721181 # ITB inst accesses
|
|
system.cpu1.itb.hits 191639831 # DTB hits
|
|
system.cpu1.itb.misses 81350 # DTB misses
|
|
system.cpu1.itb.accesses 191721181 # DTB accesses
|
|
system.cpu1.numCycles 657106376 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 80139865 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 537547218 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 121094303 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 72771731 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 544595085 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 13230640 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 1750818 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.MiscStallCycles 245014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 5964311 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 783127 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 735374 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 191409476 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 1578665 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 27162 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 640828914 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.984123 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 1.220773 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 338710091 52.85% 52.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 117550572 18.34% 71.20% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 40600676 6.34% 77.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 143967575 22.47% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 640828914 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.184284 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.818052 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 96524622 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 306596217 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 198367702 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 34666699 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 4673674 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 17189225 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 1979171 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 555902892 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 21032284 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 4673674 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 128741707 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 40944507 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 207984500 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 200380023 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 58104503 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 540647070 # Number of instructions processed by rename
|
|
system.cpu1.rename.SquashedInsts 5273833 # Number of squashed instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 8920508 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 357666 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 869250 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.SQFullEvents 25304278 # Number of times rename has blocked due to SQ full
|
|
system.cpu1.rename.FullRegisterEvents 12220 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 515542885 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 838360476 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 639083471 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 635892 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 463444914 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 52097965 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 14931648 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 13102843 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 69578208 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 89907304 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 75221964 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 8553187 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 7364919 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 519731744 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 15160501 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 524719232 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 2440222 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 49181333 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 32199370 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 264903 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 640828914 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.818813 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.060738 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 351184657 54.80% 54.80% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 125580577 19.60% 74.40% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 99945390 15.60% 89.99% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 57229371 8.93% 98.92% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 6884833 1.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 4086 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 640828914 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 51884545 43.66% 43.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 60325 0.05% 43.71% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 6398 0.01% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 32949736 27.73% 71.45% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 33928397 28.55% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 22 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 357316080 68.10% 68.10% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 1302107 0.25% 68.34% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 73183 0.01% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 41368 0.01% 68.37% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 92637950 17.65% 86.02% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 73348522 13.98% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 524719232 # Type of FU issued
|
|
system.cpu1.iq.rate 0.798530 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 118829423 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.226463 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 1810487568 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 583794764 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 509259381 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 1049453 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 417103 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 385439 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 642894662 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 653971 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 2364683 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 11367007 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 15961 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 139264 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 5290675 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 2384785 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 4103064 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 4673674 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 6987028 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 1738087 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 535009487 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 89907304 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 75221964 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 12892176 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 53410 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 1616074 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 139264 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 1829419 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 2640296 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 4469715 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 517720791 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 89804186 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 6423141 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 117242 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 161982461 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 97046647 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 72178275 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.787880 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 510319956 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 509644820 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 247330259 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 405058762 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.775590 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.610603 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 43050408 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 14895598 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 4200514 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 632658676 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.767730 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.562752 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 417403815 65.98% 65.98% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 113799591 17.99% 83.96% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 46934435 7.42% 91.38% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 15547292 2.46% 93.84% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 10981139 1.74% 95.58% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 7643765 1.21% 96.78% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 5190686 0.82% 97.60% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 3150553 0.50% 98.10% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 12007400 1.90% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 632658676 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 412964348 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 485710905 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 148471585 # Number of memory references committed
|
|
system.cpu1.commit.loads 78540296 # Number of loads committed
|
|
system.cpu1.commit.membars 3510647 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 92021861 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 377145 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 445805015 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 12220081 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 336089825 69.20% 69.20% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 1056611 0.22% 69.41% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 57564 0.01% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 35320 0.01% 69.43% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 78540296 16.17% 85.60% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 69931289 14.40% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 485710905 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 12007400 # number cycles where commit BW limit reached
|
|
system.cpu1.rob.rob_reads 1145678392 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 1065656273 # The number of ROB writes
|
|
system.cpu1.timesIdled 931363 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 16277462 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 93962526294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 412964348 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 485710905 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 1.591194 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 1.591194 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.628459 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.628459 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 611833579 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 362533704 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 622107 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 321740 # number of floating regfile writes
|
|
system.cpu1.cc_regfile_reads 111613116 # number of cc regfile reads
|
|
system.cpu1.cc_regfile_writes 112230966 # number of cc regfile writes
|
|
system.cpu1.misc_regfile_reads 1145938750 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 14868837 # number of misc regfile writes
|
|
system.cpu1.dcache.tags.replacements 5274603 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 426.947513 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 137535053 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 5275114 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 26.072432 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 8485200468500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.947513 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.833882 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.833882 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 308540922 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 308540922 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 72744707 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 72744707 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 60628902 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 60628902 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 161948 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 161948 # number of SoftPFReq hits
|
|
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50338 # number of WriteLineReq hits
|
|
system.cpu1.dcache.WriteLineReq_hits::total 50338 # number of WriteLineReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624470 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 1624470 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1636906 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 1636906 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 133373609 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 133373609 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 133535557 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 133535557 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 6201374 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 6201374 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 6969409 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 6969409 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662990 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 662990 # number of SoftPFReq misses
|
|
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447840 # number of WriteLineReq misses
|
|
system.cpu1.dcache.WriteLineReq_misses::total 447840 # number of WriteLineReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 255439 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 255439 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 200646 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 200646 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 13170783 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 13170783 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 13833773 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 13833773 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 88228717500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 88228717500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 123237994379 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 123237994379 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20350455489 # number of WriteLineReq miss cycles
|
|
system.cpu1.dcache.WriteLineReq_miss_latency::total 20350455489 # number of WriteLineReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3706894000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 3706894000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4288443500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 4288443500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6003000 # number of StoreCondFailReq miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6003000 # number of StoreCondFailReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 211466711879 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 211466711879 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 211466711879 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 211466711879 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 78946081 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 78946081 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 67598311 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 67598311 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824938 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 824938 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498178 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteLineReq_accesses::total 498178 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1879909 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 1879909 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837552 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 1837552 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 146544392 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 146544392 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 147369330 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 147369330 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.103100 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.103100 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.803685 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.803685 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.898956 # miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.898956 # miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135878 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135878 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109192 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109192 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089876 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.089876 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093871 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.093871 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14227.285356 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14227.285356 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17682.703710 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17682.703710 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45441.352914 # average WriteLineReq miss latency
|
|
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45441.352914 # average WriteLineReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14511.856060 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14511.856060 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21373.182122 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21373.182122 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16055.743374 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 16055.743374 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15286.264411 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 15286.264411 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 5662057 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 20000375 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 377912 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 710012 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.982475 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 28.169066 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 3411546 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 3411546 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3176462 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 3176462 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5650771 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 5650771 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3283 # number of WriteLineReq MSHR hits
|
|
system.cpu1.dcache.WriteLineReq_mshr_hits::total 3283 # number of WriteLineReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 129585 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 129585 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 8827233 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 8827233 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 8827233 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 8827233 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3024912 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 3024912 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1318638 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 1318638 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 662904 # number of SoftPFReq MSHR misses
|
|
system.cpu1.dcache.SoftPFReq_mshr_misses::total 662904 # number of SoftPFReq MSHR misses
|
|
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 444557 # number of WriteLineReq MSHR misses
|
|
system.cpu1.dcache.WriteLineReq_mshr_misses::total 444557 # number of WriteLineReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125854 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125854 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 200639 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 200639 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4343550 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 4343550 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5006454 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 5006454 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6436 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13289 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40779010000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40779010000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24146673124 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24146673124 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13797097500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13797097500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19809664989 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19809664989 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1736527500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1736527500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4087933500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4087933500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5874000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5874000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64925683124 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 64925683124 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78722780624 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 78722780624 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 710484000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 710484000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859770500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859770500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1570254500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1570254500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.038316 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.038316 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019507 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019507 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.803580 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.803580 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.892366 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.892366 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066947 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066947 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109188 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109188 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029640 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.029640 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033972 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.033972 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.056639 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.056639 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18311.828663 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18311.828663 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20813.115474 # average SoftPFReq mshr miss latency
|
|
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20813.115474 # average SoftPFReq mshr miss latency
|
|
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44560.461288 # average WriteLineReq mshr miss latency
|
|
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44560.461288 # average WriteLineReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13797.952389 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13797.952389 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20374.570746 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20374.570746 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14947.608091 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14947.608091 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15724.259251 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15724.259251 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110392.169049 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110392.169049 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125458.996060 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125458.996060 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118161.976070 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 118161.976070 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 5512111 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 501.811781 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 185560716 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 5512623 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 33.661057 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 8495886874000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811781 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980101 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.980101 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 388319278 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 388319278 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 185560716 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 185560716 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 185560716 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 185560716 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 185560716 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 185560716 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 5842603 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 5842603 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 5842603 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 5842603 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 5842603 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 5842603 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 60453928731 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 60453928731 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 60453928731 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 60453928731 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 60453928731 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 60453928731 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 191403319 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 191403319 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 191403319 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 191403319 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 191403319 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 191403319 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030525 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.030525 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030525 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.030525 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030525 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.030525 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10347.088230 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 10347.088230 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 10347.088230 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 10347.088230 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 8745745 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 74 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 694595 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.591143 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets 74 # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 329963 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 329963 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 329963 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 329963 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 329963 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 329963 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5512640 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 5512640 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 5512640 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 5512640 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 5512640 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 5512640 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54827935019 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 54827935019 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54827935019 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 54827935019 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54827935019 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 54827935019 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5791998 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5791998 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5791998 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 5791998 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028801 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.028801 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.028801 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9945.858068 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343 # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7331800 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.pfIdentified 7336274 # number of prefetch candidates identified
|
|
system.cpu1.l2cache.prefetcher.pfBufferHit 4099 # number of redundant prefetches already in prefetch queue
|
|
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu1.l2cache.prefetcher.pfSpanPage 897950 # number of prefetches not generated due to page crossing
|
|
system.cpu1.l2cache.tags.replacements 2207622 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 13131.101294 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 18758807 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 2223617 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 8.436168 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 9687561014000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 5032.423158 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.618743 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.333738 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3261.641393 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.864250 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 912.220012 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.307155 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004799 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005269 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199075 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229484 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055677 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.801459 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1285 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14630 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 250 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 623 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 379 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1375 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5281 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4801 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3028 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078430 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892944 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 369655582 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 369655582 # Number of data accesses
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 548671 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168948 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 717619 # number of ReadReq hits
|
|
system.cpu1.l2cache.Writeback_hits::writebacks 3411534 # number of Writeback hits
|
|
system.cpu1.l2cache.Writeback_hits::total 3411534 # number of Writeback hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70189 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::total 70189 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33871 # number of SCUpgradeReq hits
|
|
system.cpu1.l2cache.SCUpgradeReq_hits::total 33871 # number of SCUpgradeReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 868044 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 868044 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4905635 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::total 4905635 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2835466 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::total 2835466 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 174715 # number of InvalidateReq hits
|
|
system.cpu1.l2cache.InvalidateReq_hits::total 174715 # number of InvalidateReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 548671 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168948 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 4905635 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 3703510 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 9326764 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 548671 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168948 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 4905635 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 3703510 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 9326764 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11848 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8514 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 20362 # number of ReadReq misses
|
|
system.cpu1.l2cache.Writeback_misses::writebacks 12 # number of Writeback misses
|
|
system.cpu1.l2cache.Writeback_misses::total 12 # number of Writeback misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139128 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 139128 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 166752 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 166752 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 16 # number of SCUpgradeFailReq misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 16 # number of SCUpgradeFailReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 247689 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 247689 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 607002 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::total 607002 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 976114 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::total 976114 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268832 # number of InvalidateReq misses
|
|
system.cpu1.l2cache.InvalidateReq_misses::total 268832 # number of InvalidateReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11848 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8514 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 607002 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 1223803 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 1851167 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11848 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8514 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 607002 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 1223803 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 1851167 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 446786000 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 357242500 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::total 804028500 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2996930500 # number of UpgradeReq miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_miss_latency::total 2996930500 # number of UpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3475655499 # number of SCUpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3475655499 # number of SCUpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5675991 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5675991 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11909522998 # number of ReadExReq miss cycles
|
|
system.cpu1.l2cache.ReadExReq_miss_latency::total 11909522998 # number of ReadExReq miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17320734000 # number of ReadCleanReq miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17320734000 # number of ReadCleanReq miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31800458472 # number of ReadSharedReq miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31800458472 # number of ReadSharedReq miss cycles
|
|
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17606608999 # number of InvalidateReq miss cycles
|
|
system.cpu1.l2cache.InvalidateReq_miss_latency::total 17606608999 # number of InvalidateReq miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 446786000 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 357242500 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17320734000 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.data 43709981470 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::total 61834743970 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 446786000 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 357242500 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17320734000 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.data 43709981470 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::total 61834743970 # number of overall miss cycles
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560519 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 177462 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 737981 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::writebacks 3411546 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::total 3411546 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209317 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 209317 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 200623 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 200623 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 16 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 16 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115733 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 1115733 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5512637 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::total 5512637 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3811580 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::total 3811580 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 443547 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu1.l2cache.InvalidateReq_accesses::total 443547 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560519 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 177462 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 5512637 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 4927313 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 11177931 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560519 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 177462 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 5512637 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 4927313 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 11177931 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047976 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.027591 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses
|
|
system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.664676 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.664676 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.831171 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.831171 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.221997 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.221997 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110111 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110111 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.256092 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.256092 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.606096 # miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.606096 # miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047976 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110111 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.248371 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.165609 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047976 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110111 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.248371 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.165609 # miss rate for overall accesses
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41959.419779 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39486.715450 # average ReadReq miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21540.814933 # average UpgradeReq miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21540.814933 # average UpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20843.261244 # average SCUpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20843.261244 # average SCUpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354749.437500 # average SCUpgradeFailReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354749.437500 # average SCUpgradeFailReq miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48082.567244 # average ReadExReq miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48082.567244 # average ReadExReq miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28534.887859 # average ReadCleanReq miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28534.887859 # average ReadCleanReq miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32578.631668 # average ReadSharedReq miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32578.631668 # average ReadSharedReq miss latency
|
|
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 65492.980743 # average InvalidateReq miss latency
|
|
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 65492.980743 # average InvalidateReq miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41959.419779 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28534.887859 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35716.517667 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::total 33403.114884 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41959.419779 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28534.887859 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35716.517667 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::total 33403.114884 # average overall miss latency
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 2210 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 170 # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.l2cache.writebacks::writebacks 1027358 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 1027358 # number of writebacks
|
|
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 142 # number of ReadReq MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits
|
|
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 12070 # number of ReadExReq MSHR hits
|
|
system.cpu1.l2cache.ReadExReq_mshr_hits::total 12070 # number of ReadExReq MSHR hits
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3614 # number of ReadSharedReq MSHR hits
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3614 # number of ReadSharedReq MSHR hits
|
|
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits
|
|
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 142 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 15684 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::total 15828 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 142 # number of overall MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 15684 # number of overall MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::total 15828 # number of overall MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11846 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8372 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::total 20218 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 12 # number of Writeback MSHR misses
|
|
system.cpu1.l2cache.Writeback_mshr_misses::total 12 # number of Writeback MSHR misses
|
|
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104589 # number of CleanEvict MSHR misses
|
|
system.cpu1.l2cache.CleanEvict_mshr_misses::total 104589 # number of CleanEvict MSHR misses
|
|
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 722741 # number of HardPFReq MSHR misses
|
|
system.cpu1.l2cache.HardPFReq_mshr_misses::total 722741 # number of HardPFReq MSHR misses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139128 # number of UpgradeReq MSHR misses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139128 # number of UpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 166752 # number of SCUpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 166752 # number of SCUpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 16 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 16 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235619 # number of ReadExReq MSHR misses
|
|
system.cpu1.l2cache.ReadExReq_mshr_misses::total 235619 # number of ReadExReq MSHR misses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 607002 # number of ReadCleanReq MSHR misses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 607002 # number of ReadCleanReq MSHR misses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 972500 # number of ReadSharedReq MSHR misses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 972500 # number of ReadSharedReq MSHR misses
|
|
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 268829 # number of InvalidateReq MSHR misses
|
|
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 268829 # number of InvalidateReq MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11846 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8372 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 607002 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1208119 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::total 1835339 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11846 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8372 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 607002 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1208119 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 722741 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::total 2558080 # number of overall MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6503 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 13356 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 300105000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 675782000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38256632769 # number of HardPFReq MSHR miss cycles
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 38256632769 # number of HardPFReq MSHR miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2790814493 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2790814493 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2566482493 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2566482493 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4901991 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4901991 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8739513998 # number of ReadExReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8739513998 # number of ReadExReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13678722000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13678722000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25793385972 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25793385972 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15993437499 # number of InvalidateReq MSHR miss cycles
|
|
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15993437499 # number of InvalidateReq MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 300105000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13678722000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34532899970 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::total 48887403970 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 300105000 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13678722000 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34532899970 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38256632769 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::total 87144036739 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5288500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 658981000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 664269500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 808356000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 808356000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5288500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1467337000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1472625500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027396 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses
|
|
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses
|
|
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.664676 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.664676 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.831171 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.831171 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211179 # mshr miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211179 # mshr miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110111 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255144 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255144 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.606089 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.606089 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164193 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228851 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33424.770007 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average HardPFReq mshr miss latency
|
|
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52932.700330 # average HardPFReq mshr miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20059.330207 # average UpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20059.330207 # average UpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15391.014758 # average SCUpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15391.014758 # average SCUpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 306374.437500 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 306374.437500 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37091.720099 # average ReadExReq mshr miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37091.720099 # average ReadExReq mshr miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average ReadCleanReq mshr miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22534.887859 # average ReadCleanReq mshr miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26522.761925 # average ReadSharedReq mshr miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26522.761925 # average ReadSharedReq mshr miss latency
|
|
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 59492.976944 # average InvalidateReq mshr miss latency
|
|
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 59492.976944 # average InvalidateReq mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26636.716143 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34066.188993 # average overall mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102389.838409 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102148.162387 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117956.515395 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117956.515395 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 110417.412898 # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 110259.471399 # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 950963 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 10318053 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 6853 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::Writeback 7301053 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::CleanEvict 10168977 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::HardPFReq 922205 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 460948 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364065 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 477238 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 1860044 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 1122762 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5512640 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6310959 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::InvalidateReq 550275 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::InvalidateResp 443547 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16537003 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17033306 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 391276 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1237529 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 35199114 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352809840 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 540363378 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419696 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4484152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 899077066 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 11781593 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 34442064 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 1.358530 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.479569 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 22093559 64.15% 64.15% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 12348505 35.85% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 34442064 # Request fanout histogram
|
|
system.cpu1.toL2Bus.reqLayer0.occupancy 14907193441 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.snoopLayer0.occupancy 189176968 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer0.occupancy 8273171683 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer1.occupancy 7832975507 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer2.occupancy 214052518 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer3.occupancy 677527956 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 40376 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40376 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136648 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136648 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47800 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122682 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231286 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 231286 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 354048 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7339160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7497058 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 36303000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 569813871 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 92765000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 147982000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 115623 # number of replacements
|
|
system.iocache.tags.tagsinuse 11.307008 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115639 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 9081350424000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.848834 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 7.458174 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.240552 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.466136 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.706688 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1041144 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1041144 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8915 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8952 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 8915 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 8955 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 8915 # number of overall misses
|
|
system.iocache.overall_misses::total 8955 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1625113033 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 1630308033 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 12635282838 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 12635282838 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 1625113033 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 1630677033 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 1625113033 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 1630677033 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8915 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8952 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 8915 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 8955 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 8915 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 8955 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 182289.740101 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 182116.625670 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118387.703677 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 118387.703677 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 182096.821106 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 182096.821106 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 30957 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3475 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 8.908489 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 106693 # number of writebacks
|
|
system.iocache.writebacks::total 106693 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8915 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 8952 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 8915 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 8955 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 8915 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 8955 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179363033 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1182708033 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298882838 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 7298882838 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1179363033 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1182927033 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1179363033 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1182927033 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132289.740101 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 132116.625670 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68387.703677 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68387.703677 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 1604376 # number of replacements
|
|
system.l2c.tags.tagsinuse 63973.571253 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 5805157 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 1664778 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 3.487046 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 16659.203027 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 347.238411 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 480.079854 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4726.149973 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 13722.940289 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19518.694683 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 39.930664 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 37.878689 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 2515.843694 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 3528.824222 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2396.787747 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.254199 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005298 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.007325 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.072115 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.209395 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.297832 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000609 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000578 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.038389 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.053846 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036572 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.976159 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1022 10879 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 49303 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::2 1360 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::3 633 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::4 8884 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 213 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2421 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 41670 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1022 0.166000 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.752304 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 72712060 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 72712060 # Number of data accesses
|
|
system.l2c.Writeback_hits::writebacks 2536205 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 2536205 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 30090 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 27013 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 57103 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 6458 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 6165 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 12623 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 162036 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 153866 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 315902 # number of ReadExReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6626 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4489 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.inst 594958 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 614676 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296621 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6612 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4192 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.inst 566970 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 555261 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284702 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 2935107 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 6626 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 4489 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 594958 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 776712 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.l2cache.prefetcher 296621 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 6612 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 4192 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 566970 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 709127 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.l2cache.prefetcher 284702 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 3251009 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 6626 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 4489 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 594958 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 776712 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.l2cache.prefetcher 296621 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 6612 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 4192 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 566970 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 709127 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.l2cache.prefetcher 284702 # number of overall hits
|
|
system.l2c.overall_hits::total 3251009 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 47588 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 43593 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 91181 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 9906 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 10331 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 20237 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 509249 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 164886 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 674135 # number of ReadExReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2732 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2383 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.inst 65927 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 171520 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 297602 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2128 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1988 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.inst 40032 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 112082 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 243379 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 939773 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 2732 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2383 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 65927 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 680769 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.l2cache.prefetcher 297602 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 2128 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1988 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 40032 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 276968 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.l2cache.prefetcher 243379 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 1613908 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 2732 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2383 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 65927 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 680769 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.l2cache.prefetcher 297602 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 2128 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1988 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 40032 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 276968 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.l2cache.prefetcher 243379 # number of overall misses
|
|
system.l2c.overall_misses::total 1613908 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 285345500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 229148000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 514493500 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53588000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 57099500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 110687500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 66726621996 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 17979484499 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 84706106495 # number of ReadExReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 253095500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 219982000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5658543002 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 16552075998 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 202746500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 183043000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3466352000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 10969692499 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 111871010514 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 253095500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 219982000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 5658543002 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 83278697994 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 202746500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 183043000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 3466352000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 28949176998 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 196577117009 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 253095500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 219982000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 5658543002 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 83278697994 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 202746500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 183043000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 3466352000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 28949176998 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 196577117009 # number of overall miss cycles
|
|
system.l2c.Writeback_accesses::writebacks 2536205 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 2536205 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 77678 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 70606 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 148284 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 16364 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 16496 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 32860 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 671285 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 318752 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 990037 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9358 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6872 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.inst 660885 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 786196 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 594223 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8740 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6180 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.inst 607002 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 667343 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 528081 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 3874880 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 9358 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 6872 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 660885 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1457481 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 594223 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 8740 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 6180 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 607002 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 986095 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 528081 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 4864917 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 9358 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 6872 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 660885 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1457481 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 594223 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 8740 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 6180 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 607002 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 986095 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 528081 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 4864917 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.612632 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.617412 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.614908 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.605353 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.626273 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.615855 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.758618 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.517286 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.680919 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.346769 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.099756 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218164 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.321683 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.065950 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167953 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.242530 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.346769 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.099756 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.467086 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.321683 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.065950 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.280874 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.331744 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.346769 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.099756 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.467086 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.321683 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.065950 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.280874 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.331744 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5996.165000 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5256.532012 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 5642.551628 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5409.650717 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5527.006098 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 5469.560706 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 131029.461022 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109041.910769 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 125651.548273 # average ReadExReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92313.050776 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85830.433692 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96502.308757 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92073.943662 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86589.528377 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97872.026722 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 119040.460318 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92313.050776 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 85830.433692 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 122330.332307 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92073.943662 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 86589.528377 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 104521.738966 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 121801.934812 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92313.050776 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 85830.433692 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 122330.332307 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92073.943662 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 86589.528377 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 104521.738966 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 121801.934812 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 7662 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 92 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs 83.282609 # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 1246552 # number of writebacks
|
|
system.l2c.writebacks::total 1246552 # number of writebacks
|
|
system.l2c.ReadExReq_mshr_hits::cpu0.data 3 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadExReq_mshr_hits::total 3 # number of ReadExReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 217 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 87 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 35 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 178 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 73 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 8 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::total 598 # number of ReadSharedReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 217 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.data 90 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 35 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 178 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 8 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 217 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.data 90 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 35 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 178 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 8 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 601 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 52518 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 52518 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 47588 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 43593 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 91181 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9906 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10331 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 20237 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 509246 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 164886 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 674132 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2732 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2383 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65710 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 171433 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2128 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1988 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39854 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 112009 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 939175 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 2732 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 2383 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 65710 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 680679 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2128 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.itb.walker 1988 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 39854 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 276895 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 1613307 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 2732 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2383 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 65710 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 680679 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2128 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.itb.walker 1988 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 39854 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 276895 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 1613307 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6434 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 60137 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 38676 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13287 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 98813 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 990436504 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 906238506 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 1896675010 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 205762002 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 214626501 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 420388503 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 61634019996 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16330624499 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 77964644495 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 196152000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4984045002 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14830916998 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 163163000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3054573000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9843412999 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 102433066094 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 196152000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 4984045002 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 76464936994 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 163163000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 3054573000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 26174037498 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 180397710589 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 196152000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 4984045002 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 76464936994 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 163163000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 3054573000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 26174037498 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 180397710589 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4976486500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4081500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 543120500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 6844436500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4733537033 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 691840500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 5425377533 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9710023533 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4081500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1234961000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 12269814033 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.612632 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.617412 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.614908 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.605353 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.626273 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.615855 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.758614 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.517286 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.680916 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.218054 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167843 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.242375 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.467024 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.280800 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.331621 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.467024 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.280800 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.331621 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.736488 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20788.624458 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20801.208695 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20771.451847 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20774.997677 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20773.261995 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 121029.954081 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99041.910769 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 115651.896802 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86511.447609 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87880.554232 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109067.070667 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153870.709913 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84414.128070 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 113814.066215 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148745.782390 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100954.399533 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140277.627805 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151328.972695 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 92945.059080 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 124172.062714 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 60137 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1008264 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 38676 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 38676 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1353245 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 256072 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 446472 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 317458 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 117838 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 689582 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 667715 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 948127 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122682 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27002 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5660502 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 5810264 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342643 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 342643 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 6152907 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54004 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182936448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 183146836 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7268096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 190414932 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 670794 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 4218827 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 4218827 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 4218827 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 97993999 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 22746984 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 9381331556 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 8783305125 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 229295864 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.toL2Bus.trans_dist::ReadReq 60139 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 4816420 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 38676 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 3889503 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 1527175 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 497158 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 330081 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 827239 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeFailReq 247 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 1142368 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 1142368 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 4763508 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8767118 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899331 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 15666449 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271825986 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202528722 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 474354708 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 3515812 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 13605383 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.134927 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.341646 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 11769647 86.51% 86.51% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 1835736 13.49% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 13605383 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 8891301093 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 2589000 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 5132723331 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 4211299918 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 14670 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 7288 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|