Andreas Sandberg 0d1ad50326 arm: Make ID registers ISA parameters ... This patch makes the values of ID_ISARx, MIDR, and FPSID configurable as ISA parameter values. Additionally, setMiscReg now ignores writes to all of the ID registers. Note: This moves the MIDR parameter from ArmSystem to ArmISA for consistency.		2013-01-07 13:05:35 -05:00
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alpha	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00
arm	arm: Make ID registers ISA parameters	2013-01-07 13:05:35 -05:00
generic	ISA: generic Linux thread info support	2012-11-02 11:32:00 -05:00
mips	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00
noisa	cpu: add separate stats for insts/ops both globally and per cpu model	2012-02-12 16:07:39 -06:00
power	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00
sparc	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00
x86	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00
isa_parser.py	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	CPU: Merge the predecoder and decoder.	2012-05-26 13:44:46 -07:00