962 lines
109 KiB
Plaintext
962 lines
109 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000020 # Number of seconds simulated
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sim_ticks 20101000 # Number of ticks simulated
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final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 29548 # Simulator instruction rate (inst/s)
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host_op_rate 29545 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 102528509 # Simulator tick rate (ticks/s)
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host_mem_usage 221532 # Number of bytes of host memory used
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host_seconds 0.20 # Real time elapsed on the host
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sim_insts 5792 # Number of instructions simulated
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sim_ops 5792 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28416 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 444 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 71 # Per bank write bursts
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system.physmem.perBankRdBursts::1 42 # Per bank write bursts
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system.physmem.perBankRdBursts::2 55 # Per bank write bursts
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system.physmem.perBankRdBursts::3 58 # Per bank write bursts
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system.physmem.perBankRdBursts::4 53 # Per bank write bursts
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system.physmem.perBankRdBursts::5 61 # Per bank write bursts
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system.physmem.perBankRdBursts::6 52 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9 # Per bank write bursts
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system.physmem.perBankRdBursts::9 28 # Per bank write bursts
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system.physmem.perBankRdBursts::10 1 # Per bank write bursts
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system.physmem.perBankRdBursts::11 0 # Per bank write bursts
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system.physmem.perBankRdBursts::12 0 # Per bank write bursts
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system.physmem.perBankRdBursts::13 0 # Per bank write bursts
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system.physmem.perBankRdBursts::14 4 # Per bank write bursts
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system.physmem.perBankRdBursts::15 0 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 19960500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 444 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation
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system.physmem.totQLat 3861750 # Total ticks spent queuing
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system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 11.04 # Data bus utilization in percentage
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system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 357 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 44956.08 # Average gap between requests
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system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ)
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system.physmem_0.averagePower 951.571203 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ)
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system.physmem_1.averagePower 747.063003 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states
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system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu.branchPred.lookups 2330 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 660 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 9 # Number of system calls
|
|
system.cpu.numCycles 40203 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 1951 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 1916 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename
|
|
system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 4591 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 9105 # Type of FU issued
|
|
system.cpu.iq.rate 0.226476 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 252 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 14945 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3330 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1363 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1554 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.216427 # Inst execution rate
|
|
system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 8298 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 4465 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 7078 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5792 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2007 # Number of memory references committed
|
|
system.cpu.commit.loads 961 # Number of loads committed
|
|
system.cpu.commit.membars 7 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1037 # Number of branches committed
|
|
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 103 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 22278 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 21482 # The number of ROB writes
|
|
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5792 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 13740 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 7173 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2276 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 437 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 4005 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1389 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 439 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 439 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 439 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31975250 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 31975250 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 31975250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 31975250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 31975250 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 31975250 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 445 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25715250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4463750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 30179000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4367500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4367500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 25715250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8831250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 34546500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 25715250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8831250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 34546500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.982716 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 397 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 397 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 444 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 444 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|