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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Steve Reinhardt 0cf36d9409 stats: update for previous changeset 
Very small differences in IQ-specific O3 stats.
2015-04-22 20:22:29 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.625396 # Number of seconds simulated
sim_ticks 2625395606000 # Number of ticks simulated
final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 91005 # Simulator instruction rate (inst/s)
host_op_rate 110413 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1985416078 # Simulator tick rate (ticks/s)
host_mem_usage 586088 # Number of bytes of host memory used
host_seconds 1322.34 # Real time elapsed on the host
sim_insts 120339436 # Number of instructions simulated
sim_ops 146004136 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1180896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1238652 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8338496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 327120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 750304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 683328 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12522572 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1180896 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 327120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1508016 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8921792 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8939536 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 20697 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 19879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 130289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5178 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 11747 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 10677 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 198526 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 139403 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143839 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 683 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 449797 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 471796 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 3176091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 124598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 285787 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 260276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4769785 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 449797 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 124598 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 574396 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3398266 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6743 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3405024 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3398266 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 683 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 449797 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 478540 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 3176091 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 124598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 285802 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 260276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 8174809 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198527 # Number of read requests accepted
system.physmem.writeReqs 180063 # Number of write requests accepted
system.physmem.readBursts 198527 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 180063 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12696000 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue
system.physmem.bytesWritten 10018560 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12522636 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 11257872 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 23492 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 14407 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12827 # Per bank write bursts
system.physmem.perBankRdBursts::1 12491 # Per bank write bursts
system.physmem.perBankRdBursts::2 12947 # Per bank write bursts
system.physmem.perBankRdBursts::3 12890 # Per bank write bursts
system.physmem.perBankRdBursts::4 14947 # Per bank write bursts
system.physmem.perBankRdBursts::5 12185 # Per bank write bursts
system.physmem.perBankRdBursts::6 12844 # Per bank write bursts
system.physmem.perBankRdBursts::7 12385 # Per bank write bursts
system.physmem.perBankRdBursts::8 12025 # Per bank write bursts
system.physmem.perBankRdBursts::9 12120 # Per bank write bursts
system.physmem.perBankRdBursts::10 11888 # Per bank write bursts
system.physmem.perBankRdBursts::11 11181 # Per bank write bursts
system.physmem.perBankRdBursts::12 11694 # Per bank write bursts
system.physmem.perBankRdBursts::13 12452 # Per bank write bursts
system.physmem.perBankRdBursts::14 11831 # Per bank write bursts
system.physmem.perBankRdBursts::15 11668 # Per bank write bursts
system.physmem.perBankWrBursts::0 10196 # Per bank write bursts
system.physmem.perBankWrBursts::1 10156 # Per bank write bursts
system.physmem.perBankWrBursts::2 10450 # Per bank write bursts
system.physmem.perBankWrBursts::3 10103 # Per bank write bursts
system.physmem.perBankWrBursts::4 9839 # Per bank write bursts
system.physmem.perBankWrBursts::5 9619 # Per bank write bursts
system.physmem.perBankWrBursts::6 10216 # Per bank write bursts
system.physmem.perBankWrBursts::7 9774 # Per bank write bursts
system.physmem.perBankWrBursts::8 9494 # Per bank write bursts
system.physmem.perBankWrBursts::9 9611 # Per bank write bursts
system.physmem.perBankWrBursts::10 9445 # Per bank write bursts
system.physmem.perBankWrBursts::11 9199 # Per bank write bursts
system.physmem.perBankWrBursts::12 9616 # Per bank write bursts
system.physmem.perBankWrBursts::13 9900 # Per bank write bursts
system.physmem.perBankWrBursts::14 9667 # Per bank write bursts
system.physmem.perBankWrBursts::15 9255 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 63 # Number of times write queue was full causing retry
system.physmem.totGap 2625395343000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 559 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 3083 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 194857 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4436 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 175627 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 60901 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 71603 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 16635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12571 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8573 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7706 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6473 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4946 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1315 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 955 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 741 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 319 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 264 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3392 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9461 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8415 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9026 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 11942 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9626 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8927 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1572 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1432 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1535 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1780 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2392 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1974 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1757 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1375 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 811 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 446 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 449 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 224 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 91717 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 247.658515 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 138.206739 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 311.047088 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 48645 53.04% 53.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18050 19.68% 72.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5879 6.41% 79.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3418 3.73% 82.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2896 3.16% 86.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1497 1.63% 87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 939 1.02% 88.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1042 1.14% 89.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9351 10.20% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 91717 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6649 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 29.834862 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 569.193500 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6647 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6649 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6649 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 23.543390 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.659302 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 38.965105 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 6283 94.50% 94.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 92 1.38% 95.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 34 0.51% 96.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 28 0.42% 96.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 36 0.54% 97.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 35 0.53% 98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 13 0.20% 98.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 17 0.26% 98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 4 0.06% 98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 17 0.26% 98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 15 0.23% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 12 0.18% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271 5 0.08% 99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 5 0.08% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 1 0.02% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 2 0.03% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 5 0.08% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 4 0.06% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 13 0.20% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383 1 0.02% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431 2 0.03% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 3 0.05% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559 1 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-687 2 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6649 # Writes before turning the bus around for reads
system.physmem.totQLat 7005041065 # Total ticks spent queuing
system.physmem.totMemAccLat 10724572315 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 991875000 # Total ticks spent in databus transfers
system.physmem.avgQLat 35312.12 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 54062.12 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.77 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.29 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.07 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.13 # Average write queue length when enqueuing
system.physmem.readRowHits 165504 # Number of row buffer hits during reads
system.physmem.writeRowHits 97693 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 62.40 # Row buffer hit rate for writes
system.physmem.avgGap 6934666.38 # Average gap between requests
system.physmem.pageHitRate 74.15 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 361050480 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 197001750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 807424800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 520687440 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 75248496990 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1509227374500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1757839822440 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.553437 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2510629171267 # Time in different power states
system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 27094642483 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 332330040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 181330875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 739892400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 493691760 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 74790166545 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1509629418750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1757644616850 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.479084 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2511304272827 # Time in different power states
system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 26423733173 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 51768532 # Number of BP lookups
system.cpu0.branchPred.condPredicted 23412360 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 919881 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 31255966 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 23302169 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 74.552708 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 15318582 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 29481 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 62660 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 62660 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24194 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18908 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 19558 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 43102 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 433.564568 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 2585.553866 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-4095 41662 96.66% 96.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::4096-8191 436 1.01% 97.67% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-12287 432 1.00% 98.67% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::12288-16383 320 0.74% 99.42% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-20479 76 0.18% 99.59% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::20480-24575 60 0.14% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-28671 79 0.18% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::28672-32767 9 0.02% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-36863 4 0.01% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-45055 16 0.04% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::45056-49151 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-53247 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 43102 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 15681 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 9053.791276 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 7430.926564 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 8773.860990 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 14744 94.02% 94.02% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 873 5.57% 99.59% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 41 0.26% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991 10 0.06% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375 7 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 15681 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 91363987860 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.449877 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.503999 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 91318747860 99.95% 99.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 34013000 0.04% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 5422000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 3241000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 1011500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 587500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 452000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 12000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 91363987860 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5167 76.75% 76.75% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1565 23.25% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6732 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62660 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62660 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6732 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6732 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 69392 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 22710900 # DTB read hits
system.cpu0.dtb.read_misses 53664 # DTB read misses
system.cpu0.dtb.write_hits 16914206 # DTB write hits
system.cpu0.dtb.write_misses 8996 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3521 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 84 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1885 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 828 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 22764564 # DTB read accesses
system.cpu0.dtb.write_accesses 16923202 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 39625106 # DTB hits
system.cpu0.dtb.misses 62660 # DTB misses
system.cpu0.dtb.accesses 39687766 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 9923 # Table walker walks requested
system.cpu0.itb.walker.walksShort 9923 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3743 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6075 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 105 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 9818 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 399.113872 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 2107.706971 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 9439 96.14% 96.14% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 239 2.43% 98.57% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 79 0.80% 99.38% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 28 0.29% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 10 0.10% 99.77% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 11 0.11% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767 5 0.05% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 9818 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2687 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10340.528470 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 8874.826622 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 6037.575177 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 928 34.54% 34.54% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1618 60.22% 94.75% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 45 1.67% 96.43% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.16% 99.59% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2687 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 18349502828 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.974755 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.157116 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 463854500 2.53% 2.53% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 17885129828 97.47% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 423500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 95000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 18349502828 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2262 87.61% 87.61% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 320 12.39% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2582 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9923 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2582 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 12505 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 70918524 # ITB inst hits
system.cpu0.itb.inst_misses 9923 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 70928447 # ITB inst accesses
system.cpu0.itb.hits 70918524 # DTB hits
system.cpu0.itb.misses 9923 # DTB misses
system.cpu0.itb.accesses 70928447 # DTB accesses
system.cpu0.numCycles 192710246 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 19172907 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 190300440 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 51768532 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 38620751 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 166603353 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 5605830 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 133760 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 54794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 348448 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 420234 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 74628 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 70919147 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 257234 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 4157 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 189611039 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.227807 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.311092 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 87830492 46.32% 46.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 29214542 15.41% 61.73% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 14106780 7.44% 69.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 58459225 30.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 189611039 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.268634 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.987495 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 24427882 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 101305691 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 56642715 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4754811 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2479940 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 2942193 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 327073 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 148781526 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3762312 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 2479940 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 32842566 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 11912016 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 79322122 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 52855770 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 10198625 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 132285921 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1008096 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1377906 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 148604 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 51873 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 6170558 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 135790293 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 611071310 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 146878490 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9376 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 124889963 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 10900327 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 2656202 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 2518524 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 22032615 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 23644678 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 18416726 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1638849 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2450280 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 129422072 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1660998 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 127592349 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 453825 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10488941 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 21267672 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 117222 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 189611039 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.672916 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 0.964306 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 115784330 61.06% 61.06% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 32509497 17.15% 78.21% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 29946391 15.79% 94.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 10293248 5.43% 99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1077539 0.57% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 189611039 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 10302435 44.02% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 127 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 44.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5400760 23.08% 67.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 7700326 32.90% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 86139109 67.51% 67.51% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 105637 0.08% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 7185 0.01% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.60% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 23381898 18.33% 85.93% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 17956248 14.07% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 127592349 # Type of FU issued
system.cpu0.iq.rate 0.662094 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 23403648 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.183425 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 468620138 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 141579564 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 124128658 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 33072 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11274 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 150972031 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 21694 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 349342 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1883137 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2543 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 18891 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 974261 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 112825 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 327783 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 2479940 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1553148 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 173644 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 131254258 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 23644678 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 18416726 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 851019 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 171188 # number of nop insts executed
system.cpu0.iew.exec_refs 40733276 # number of memory reference insts executed
system.cpu0.iew.exec_branches 24565455 # Number of branches executed
system.cpu0.iew.exec_stores 17777509 # Number of stores executed
system.cpu0.iew.exec_rate 0.656753 # Inst execution rate
system.cpu0.iew.wb_sent 126045909 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 124138382 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 63204033 # num instructions producing a value
system.cpu0.iew.wb_consumers 102166760 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.644171 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.618636 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 9496881 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1543776 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 596906 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 186488308 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.647310 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.345681 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 128655160 68.99% 68.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 31929494 17.12% 86.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 12238036 6.56% 92.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3079239 1.65% 94.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 4650991 2.49% 96.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 2566190 1.38% 98.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1394957 0.75% 98.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 526048 0.28% 99.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1448193 0.78% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 186488308 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 99634335 # Number of instructions committed
system.cpu0.commit.committedOps 120715819 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 39204006 # Number of memory references committed
system.cpu0.commit.loads 21761541 # Number of loads committed
system.cpu0.commit.membars 628761 # Number of memory barriers committed
system.cpu0.commit.branches 23967170 # Number of branches committed
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 105564175 # Number of committed integer instructions.
system.cpu0.commit.function_calls 4749359 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 81401150 67.43% 67.43% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 103478 0.09% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 7185 0.01% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 21761541 18.03% 85.55% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 17442465 14.45% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 120715819 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1448193 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 292184577 # The number of ROB reads
system.cpu0.rob.rob_writes 263546817 # The number of ROB writes
system.cpu0.timesIdled 122559 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 3099207 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5058081346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 99512641 # Number of Instructions Simulated
system.cpu0.committedOps 120594125 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.936540 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.936540 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.516385 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.516385 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 137143613 # number of integer regfile reads
system.cpu0.int_regfile_writes 78685231 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8206 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
system.cpu0.cc_regfile_reads 446712527 # number of cc regfile reads
system.cpu0.cc_regfile_writes 47224279 # number of cc regfile writes
system.cpu0.misc_regfile_reads 373664445 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1193481 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 673244 # number of replacements
system.cpu0.dcache.tags.tagsinuse 484.859625 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 36215686 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 673756 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 53.751931 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 278115000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.859625 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946991 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.946991 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 77975696 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 77975696 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 20636575 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 20636575 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 14390339 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 14390339 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296451 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 296451 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354772 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 354772 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351523 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 351523 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 35026914 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 35026914 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 35323365 # number of overall hits
system.cpu0.dcache.overall_hits::total 35323365 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 606585 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 606585 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1800589 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1800589 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141770 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 141770 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24267 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 24267 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21226 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 21226 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2407174 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2407174 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2548944 # number of overall misses
system.cpu0.dcache.overall_misses::total 2548944 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8152337496 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 8152337496 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26333386263 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 26333386263 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385690944 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 385690944 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485736540 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 485736540 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 421500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 421500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 34485723759 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 34485723759 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 34485723759 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 34485723759 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 21243160 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 21243160 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 16190928 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 16190928 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438221 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 438221 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379039 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 379039 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372749 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 372749 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 37434088 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 37434088 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 37872309 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 37872309 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028554 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.028554 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111210 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.111210 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323513 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323513 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064022 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064022 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056944 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056944 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064304 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.064304 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067304 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.067304 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13439.728144 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13439.728144 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14624.873451 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 14624.873451 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15893.639263 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15893.639263 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22884.035617 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22884.035617 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14326.228083 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14326.228083 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13529.416009 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13529.416009 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 842 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 3715311 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 190617 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.541667 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 19.490974 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 491598 # number of writebacks
system.cpu0.dcache.writebacks::total 491598 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 240080 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 240080 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1488537 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1488537 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18067 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18067 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1728617 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1728617 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1728617 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1728617 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366505 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 366505 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312052 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 312052 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98413 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 98413 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6200 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6200 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21226 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 21226 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 678557 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 678557 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 776970 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 776970 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4125978302 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4125978302 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5242118761 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5242118761 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570027702 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570027702 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93210251 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93210251 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452955960 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452955960 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 405000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 405000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9368097063 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9368097063 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10938124765 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10938124765 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5613897000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5613897000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4260937012 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4260937012 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9874834012 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9874834012 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017253 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019273 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019273 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224574 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224574 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016357 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016357 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056944 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056944 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018127 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.018127 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020516 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.020516 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11257.631689 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11257.631689 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16798.862885 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16798.862885 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15953.458405 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.458405 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15033.911452 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15033.911452 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21339.675869 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21339.675869 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13805.910282 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13805.910282 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14077.924199 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14077.924199 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1204763 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.748349 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 69666497 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1205275 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 57.801329 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6415532250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748349 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 143036633 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 143036633 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 69666497 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 69666497 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 69666497 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 69666497 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 69666497 # number of overall hits
system.cpu0.icache.overall_hits::total 69666497 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1249171 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1249171 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1249171 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1249171 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1249171 # number of overall misses
system.cpu0.icache.overall_misses::total 1249171 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12316352733 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 12316352733 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 12316352733 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 12316352733 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 12316352733 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 12316352733 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 70915668 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 70915668 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 70915668 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 70915668 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 70915668 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 70915668 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017615 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.017615 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017615 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.017615 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017615 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.017615 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.621087 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.621087 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9859.621087 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9859.621087 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1363430 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 975 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 105819 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.884548 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 88.636364 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43872 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 43872 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 43872 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 43872 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 43872 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 43872 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1205299 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1205299 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1205299 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1205299 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1205299 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1205299 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10580120186 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10580120186 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10580120186 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10580120186 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10580120186 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10580120186 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265434748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016996 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.016996 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.016996 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8778.004616 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762691 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1767870 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 4580 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 220490 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 265715 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16040.758095 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2094535 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 281946 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 7.428852 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 2609861933500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 9327.683600 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 17.267794 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.026625 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4039.749605 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1610.171801 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1044.858671 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.569317 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001054 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.246567 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.098277 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063773 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.979050 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1077 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15140 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 37 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 401 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 317 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4738 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7052 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2870 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065735 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924072 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 41668980 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 41668980 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50191 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11923 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1155240 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 372543 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 1589897 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 491596 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 491596 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28444 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 28444 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1603 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1603 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210600 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 210600 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50191 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11923 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1155240 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 583143 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1800497 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50191 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11923 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1155240 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 583143 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1800497 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 425 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 170 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 50043 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 98477 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 149115 # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27382 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 27382 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19621 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 19621 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45870 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 45870 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 425 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 170 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 50043 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 144347 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 194985 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 425 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 170 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 50043 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 144347 # number of overall misses
system.cpu0.l2cache.overall_misses::total 194985 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11462248 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4075246 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2454493202 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2862988088 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 5333018784 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502169231 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 502169231 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396029410 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396029410 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 393499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 393499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2652639758 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2652639758 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11462248 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4075246 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2454493202 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5515627846 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 7985658542 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11462248 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4075246 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2454493202 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5515627846 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 7985658542 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50616 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12093 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1205283 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 471020 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 1739012 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 491597 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 491597 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55826 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55826 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21224 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 21224 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256470 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 256470 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50616 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12093 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1205283 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 727490 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 1995482 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50616 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12093 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1205283 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 727490 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 1995482 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014058 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.041520 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.209072 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.085747 # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.490488 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.490488 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924472 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924472 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178851 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178851 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014058 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041520 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198418 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.097713 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014058 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041520 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198418 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.097713 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23972.035294 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49047.683033 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29072.657453 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35764.468927 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18339.391973 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18339.391973 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20183.956475 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20183.956475 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 196749.500000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 196749.500000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57829.512928 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57829.512928 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 40955.245491 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 40955.245491 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.400000 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 193170 # number of writebacks
system.cpu0.l2cache.writebacks::total 193170 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 27 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 699 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 728 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6075 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 6075 # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 27 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6774 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 6803 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 27 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6774 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 6803 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 424 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 169 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 50016 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97778 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 148387 # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 232167 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27382 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27382 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19621 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19621 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39795 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 39795 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 424 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 169 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50016 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137573 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 188182 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 424 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 169 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50016 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137573 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 420349 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2961750 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2122401548 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2188318454 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4322363002 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15144909271 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 533487187 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 533487187 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293580560 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293580560 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 321999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 321999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1622773486 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1622773486 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2961750 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2122401548 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3811091940 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 5945136488 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2961750 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2122401548 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3811091940 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 21090045759 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 241524750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5378380500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5619905250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4060847435 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4060847435 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9439227935 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9680752685 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.207588 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.085328 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.490488 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.490488 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924472 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924472 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155164 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155164 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094304 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210650 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22380.478778 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29128.987054 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65232.824954 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19483.134431 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19483.134431 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14962.568676 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.568676 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 160999.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 160999.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40778.326071 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40778.326071 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31592.482214 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50172.703537 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 1908189 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1835262 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 26172 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 26172 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 491597 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 299764 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 91875 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43573 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 114693 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 284602 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 270315 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2416584 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2311982 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27986 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112626 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 4869178 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77186016 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82205272 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48372 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202464 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 159642124 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 659500 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 3123483 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 3.174208 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.379288 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 2579348 82.58% 82.58% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 544135 17.42% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3123483 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 1823730646 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 112580498 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1815085939 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1180413157 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 15906731 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 62058933 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 6179090 # Number of BP lookups
system.cpu1.branchPred.condPredicted 3881916 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 362855 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 3346788 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 2458848 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 73.468890 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 1048082 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 10606 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 24514 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 24514 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11457 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6002 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 7055 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 17459 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 393.464689 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 2513.400268 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 16937 97.01% 97.01% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 156 0.89% 97.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 187 1.07% 98.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 85 0.49% 99.46% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 23 0.13% 99.59% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 6 0.03% 99.63% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 44 0.25% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 3 0.02% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 17459 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5476 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 9377.190285 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 8039.034346 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 5934.391980 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 2488 45.43% 45.43% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2481 45.31% 90.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 381 6.96% 97.70% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 96 1.75% 99.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 6 0.11% 99.56% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 20 0.37% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 5476 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 69614954880 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.366193 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.484439 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 44157971700 63.43% 63.43% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 25439149180 36.54% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 11249000 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 3199000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 940000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 768000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 744500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 290500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 107000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 122500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 85500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 64000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 71500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 26500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 31000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 135000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 69614954880 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1964 73.78% 73.78% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 698 26.22% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2662 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24514 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24514 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2662 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2662 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 27176 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 5241297 # DTB read hits
system.cpu1.dtb.read_misses 21288 # DTB read misses
system.cpu1.dtb.write_hits 4318497 # DTB write hits
system.cpu1.dtb.write_misses 3226 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 72 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 621 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 379 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 5262585 # DTB read accesses
system.cpu1.dtb.write_accesses 4321723 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 9559794 # DTB hits
system.cpu1.dtb.misses 24514 # DTB misses
system.cpu1.dtb.accesses 9584308 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 6863 # Table walker walks requested
system.cpu1.itb.walker.walksShort 6863 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4096 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2697 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 70 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 6793 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 193.655233 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 1558.039702 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-2047 6647 97.85% 97.85% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::2048-4095 36 0.53% 98.38% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 98.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::6144-8191 24 0.35% 99.15% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-10239 16 0.24% 99.38% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::10240-12287 12 0.18% 99.56% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-14335 8 0.12% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.07% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-18431 3 0.04% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.04% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.06% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::30720-32767 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 6793 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1235 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10095.547368 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 8796.441001 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5908.625766 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095 181 14.66% 14.66% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.17% 28.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287 552 44.70% 73.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383 256 20.73% 94.25% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.57% 94.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575 7 0.57% 95.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.27% 97.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767 18 1.46% 99.11% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.24% 99.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.40% 99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.16% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1235 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 18043801328 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.988843 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.105174 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 201557764 1.12% 1.12% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 17842013064 98.88% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 213500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 17000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 18043801328 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6863 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6863 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 8028 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 10532607 # ITB inst hits
system.cpu1.itb.inst_misses 6863 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1195 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 10539470 # ITB inst accesses
system.cpu1.itb.hits 10532607 # DTB hits
system.cpu1.itb.misses 6863 # DTB misses
system.cpu1.itb.accesses 10539470 # DTB accesses
system.cpu1.numCycles 43132973 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 9545781 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 31669827 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 6179090 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 3506930 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 31408441 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 995212 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 85708 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 38872 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 217286 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 331419 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 27804 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 10531999 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 133008 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2352 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 42152917 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.913975 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.225517 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 24362526 57.80% 57.80% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 6315176 14.98% 72.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 2214119 5.25% 78.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 9261096 21.97% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 42152917 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.143257 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.734237 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 8274124 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 20645023 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 11553748 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1337865 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 342157 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 880050 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 158552 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 30233981 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1392367 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 342157 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 10058392 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2609511 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 14923378 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 11073163 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3146316 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 28748329 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 284293 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 329352 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 50565 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 19779 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1931384 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 29150261 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 132893523 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 32973401 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1672 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 25705063 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 3445198 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 453540 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 375844 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 3445196 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 5586646 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 4747027 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 699100 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 721726 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 27759685 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 627473 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 27258527 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 145234 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2977146 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 6943190 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 53970 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 42152917 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.646658 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.966330 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 26379254 62.58% 62.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 7348926 17.43% 80.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 5684884 13.49% 93.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 2419597 5.74% 99.24% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 320238 0.76% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 42152917 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 2004888 32.52% 32.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 611 0.01% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1891782 30.69% 63.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 2267092 36.78% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 17154225 62.93% 62.93% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 35391 0.13% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 4079 0.01% 63.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 5491685 20.15% 83.22% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 4573079 16.78% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 27258527 # Type of FU issued
system.cpu1.iq.rate 0.631965 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 6164373 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.226145 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 102973934 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 31372858 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 26623969 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 5644 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2050 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 33419259 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 3574 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 107638 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 606025 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 849 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 10642 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 402770 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 45923 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 97906 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 342157 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 666539 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 117242 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 28442190 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 5586646 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 4747027 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 329140 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 12736 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 94970 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 10642 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 72014 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 152187 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 224201 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 26920844 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 5360548 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 313188 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 55032 # number of nop insts executed
system.cpu1.iew.exec_refs 9857010 # number of memory reference insts executed
system.cpu1.iew.exec_branches 4125375 # Number of branches executed
system.cpu1.iew.exec_stores 4496462 # Number of stores executed
system.cpu1.iew.exec_rate 0.624136 # Inst execution rate
system.cpu1.iew.wb_sent 26746276 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 26625754 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 13483465 # num instructions producing a value
system.cpu1.iew.wb_consumers 21315020 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.617295 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.632580 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 2680688 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 573503 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 207406 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 41589167 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.611775 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.358099 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 29454101 70.82% 70.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 7064012 16.99% 87.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 2119517 5.10% 92.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 873586 2.10% 95.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 770133 1.85% 96.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 442153 1.06% 97.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 274514 0.66% 98.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 148169 0.36% 98.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 442982 1.07% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 41589167 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 20860008 # Number of instructions committed
system.cpu1.commit.committedOps 25443224 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 9324878 # Number of memory references committed
system.cpu1.commit.loads 4980621 # Number of loads committed
system.cpu1.commit.membars 230323 # Number of memory barriers committed
system.cpu1.commit.branches 3917567 # Number of branches committed
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 22363157 # Number of committed integer instructions.
system.cpu1.commit.function_calls 552505 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 16079933 63.20% 63.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 34334 0.13% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 4079 0.02% 63.35% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.35% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.35% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.35% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 4980621 19.58% 82.93% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 4344257 17.07% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 25443224 # Class of committed instruction
system.cpu1.commit.bw_lim_events 442982 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 68115809 # The number of ROB reads
system.cpu1.rob.rob_writes 56808236 # The number of ROB writes
system.cpu1.timesIdled 67589 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 980056 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5207108948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 20826795 # Number of Instructions Simulated
system.cpu1.committedOps 25410011 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.071033 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.071033 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.482851 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.482851 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 30054591 # number of integer regfile reads
system.cpu1.int_regfile_writes 16942565 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1393 # number of floating regfile reads
system.cpu1.fp_regfile_writes 518 # number of floating regfile writes
system.cpu1.cc_regfile_reads 96178951 # number of cc regfile reads
system.cpu1.cc_regfile_writes 9490884 # number of cc regfile writes
system.cpu1.misc_regfile_reads 81077063 # number of misc regfile reads
system.cpu1.misc_regfile_writes 422777 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 228827 # number of replacements
system.cpu1.dcache.tags.tagsinuse 478.548130 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 8439386 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 229141 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 36.830537 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 103436351500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.548130 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934664 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.934664 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 18658844 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 18658844 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 4567362 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 4567362 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 3580643 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 3580643 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63652 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 63652 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87547 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 87547 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79571 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 79571 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 8148005 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 8148005 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 8211657 # number of overall hits
system.cpu1.dcache.overall_hits::total 8211657 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 253908 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 253908 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 480072 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 480072 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 36130 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 36130 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19184 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 19184 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23489 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23489 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 733980 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 733980 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 770110 # number of overall misses
system.cpu1.dcache.overall_misses::total 770110 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4026677920 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 4026677920 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11127636122 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 11127636122 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 374723986 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 374723986 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547048827 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 547048827 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1003000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1003000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 15154314042 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 15154314042 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 15154314042 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 15154314042 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 4821270 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 4821270 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4060715 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 4060715 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99782 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 99782 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106731 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 106731 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103060 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 103060 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 8881985 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 8881985 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 8981767 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 8981767 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.052664 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.052664 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118224 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.118224 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.362089 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.362089 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179742 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179742 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227916 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227916 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.082637 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.082637 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.085741 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.085741 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15858.806812 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15858.806812 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23179.098389 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 23179.098389 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19533.151897 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19533.151897 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23289.574993 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23289.574993 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20646.766999 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20646.766999 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19678.116168 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 19678.116168 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1600979 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 49143 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.363636 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 32.577966 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 137785 # number of writebacks
system.cpu1.dcache.writebacks::total 137785 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 90105 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 90105 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375217 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 375217 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13775 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13775 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 465322 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 465322 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 465322 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 465322 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163803 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 163803 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104855 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 104855 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32523 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 32523 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5409 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5409 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23489 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23489 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 268658 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 268658 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 301181 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 301181 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2171865461 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2171865461 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2612489394 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2612489394 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 519825898 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 519825898 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98469253 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98469253 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 510672173 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 510672173 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 974500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 974500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4784354855 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4784354855 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5304180753 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5304180753 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 979094500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 979094500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848774501 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848774501 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827869001 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827869001 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033975 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033975 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025822 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025822 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.325941 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.325941 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050679 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050679 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227916 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227916 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030248 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030248 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033532 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13259.009060 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13259.009060 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24915.258157 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24915.258157 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15983.331734 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15983.331734 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18204.705676 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18204.705676 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21740.907361 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21740.907361 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17808.346876 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17808.346876 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17611.272799 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17611.272799 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 667401 # number of replacements
system.cpu1.icache.tags.tagsinuse 498.527528 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 9840970 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 667913 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 14.733910 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 78865217000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.527528 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973687 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.973687 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 21731377 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 21731377 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 9840970 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 9840970 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 9840970 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 9840970 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 9840970 # number of overall hits
system.cpu1.icache.overall_hits::total 9840970 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 690756 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 690756 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 690756 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 690756 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 690756 # number of overall misses
system.cpu1.icache.overall_misses::total 690756 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6328356335 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6328356335 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6328356335 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6328356335 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6328356335 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6328356335 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 10531726 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 10531726 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 10531726 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 10531726 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 10531726 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 10531726 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065588 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.065588 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065588 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.065588 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065588 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.065588 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9161.493110 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9161.493110 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9161.493110 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9161.493110 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 590927 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 49303 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.985620 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22831 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 22831 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 22831 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 22831 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 22831 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 22831 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 667925 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 667925 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 667925 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 667925 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 667925 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 667925 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5443930957 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5443930957 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5443930957 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5443930957 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5443930957 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5443930957 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8774500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8774500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8774500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 8774500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063420 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.063420 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.063420 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8150.512343 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 270002 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 271052 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 936 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 67932 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 66588 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15581.068012 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 931760 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 81198 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 11.475159 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 6676.895279 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 16.747734 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010823 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4682.837977 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2664.181165 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.395034 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.407525 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001022 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285818 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.162609 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093896 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.950993 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1283 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13300 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 906 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 364 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 471 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8616 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4213 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078308 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001648 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811768 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 18862163 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 18862163 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19502 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7394 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 645640 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 128208 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 800744 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 137784 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 137784 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2324 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 2324 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1121 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38121 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 38121 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19502 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7394 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 645640 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 166329 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 838865 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19502 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7394 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 645640 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 166329 # number of overall hits
system.cpu1.l2cache.overall_hits::total 838865 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 440 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 275 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22267 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 73501 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 96483 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29168 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29168 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22368 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22368 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35878 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 35878 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 440 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 275 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 22267 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 109379 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 132361 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 440 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 275 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 22267 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 109379 # number of overall misses
system.cpu1.l2cache.overall_misses::total 132361 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9737996 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5511500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 907046728 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1743519842 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 2665816066 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555344240 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 555344240 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449490983 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449490983 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 955500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 955500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1553872219 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1553872219 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9737996 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5511500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 907046728 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3297392061 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 4219688285 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9737996 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5511500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 907046728 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3297392061 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 4219688285 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19942 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7669 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 667907 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201709 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 897227 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 137784 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 137784 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31492 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 31492 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23489 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23489 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73999 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 73999 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19942 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7669 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 667907 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 275708 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 971226 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19942 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7669 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 667907 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 275708 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 971226 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035859 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.033338 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.364391 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.107535 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926203 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926203 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952276 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952276 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484844 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484844 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035859 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033338 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.396720 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.136282 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035859 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033338 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.396720 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.136282 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20041.818182 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 40735.021691 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23721.035659 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27629.904398 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19039.503566 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19039.503566 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20095.269269 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20095.269269 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43309.889598 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43309.889598 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31880.148118 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31880.148118 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 39082 # number of writebacks
system.cpu1.l2cache.writebacks::total 39082 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 149 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 867 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 867 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1016 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1016 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 1048 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 439 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22249 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 73352 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 96302 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 37405 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29168 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29168 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22368 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22368 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35011 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 35011 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 439 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22249 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108363 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 131313 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 439 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22249 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108363 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 168718 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3646000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 759958022 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1259838411 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 2030303933 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619373742 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484903709 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484903709 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 334604857 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 334604857 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 832000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 832000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1217604967 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1217604967 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3646000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 759958022 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2477443378 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 3247908900 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3646000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 759958022 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2477443378 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4867282642 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7975000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 934007000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941982000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811858998 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811858998 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7975000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1745865998 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1753840998 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.363653 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.107333 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926203 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926203 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952276 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952276 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.473128 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.473128 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135203 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173717 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 17175.242815 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21082.676715 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43292.975324 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16624.510045 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16624.510045 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.086955 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.086955 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34777.783182 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34777.783182 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24734.100203 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28848.626951 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 1243272 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 949021 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 4907 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 4907 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 137784 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 47376 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 75841 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43101 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 89718 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 96830 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 79934 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1336034 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 901614 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17159 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 43403 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2298210 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42747664 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29480945 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 79768 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 72339053 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 592219 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1674781 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 3.301785 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.459032 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 1169358 69.82% 69.82% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 505423 30.18% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1674781 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 730243456 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 87400998 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 1002964345 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 454923751 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 9604282 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 23499938 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31011 # Transaction distribution
system.iobus.trans_dist::ReadResp 31011 # Transaction distribution
system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
system.iobus.trans_dist::WriteResp 23197 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 198996708 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36791507 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
system.iocache.tags.tagsinuse 14.446927 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 254830116000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.446927 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.902933 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.902933 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 32290377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 32290377 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6656632824 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 6656632824 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide 32290377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 32290377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 32290377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 32290377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128136.416667 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128136.416667 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183763.052783 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183763.052783 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128136.416667 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128136.416667 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 23055 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3532 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6.527463 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19155377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 19155377 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772970838 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772970838 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 19155377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 19155377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 19155377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 19155377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76013.400794 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76013.400794 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131762.666685 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131762.666685 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 136223 # number of replacements
system.l2c.tags.tagsinuse 64041.513044 # Cycle average of tags in use
system.l2c.tags.total_refs 356136 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 200557 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 1.775735 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 12781.567033 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.527645 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.082100 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5930.123644 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 1752.659752 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33401.860992 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.992291 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903251 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3387.143441 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1822.858320 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4939.794575 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.195031 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000237 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000017 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.090487 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.026743 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.509672 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000122 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.051684 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.027815 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.075375 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.977196 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 31391 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 32916 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 6119 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 25156 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4913 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 27508 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.478989 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.502258 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5099427 # Number of tag accesses
system.l2c.tags.data_accesses 5099427 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 187 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 89 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 32294 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 45191 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 42802 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 60 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 34 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 17148 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11819 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7598 # number of ReadReq hits
system.l2c.ReadReq_hits::total 157222 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 232253 # number of Writeback hits
system.l2c.Writeback_hits::total 232253 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2477 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 788 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3265 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 61 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3656 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1776 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5432 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 187 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 32294 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 48847 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 42802 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 60 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 17148 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 13595 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 7598 # number of demand (read+write) hits
system.l2c.demand_hits::total 162654 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 187 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits
system.l2c.overall_hits::cpu0.inst 32294 # number of overall hits
system.l2c.overall_hits::cpu0.data 48847 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 42802 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 60 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits
system.l2c.overall_hits::cpu1.inst 17148 # number of overall hits
system.l2c.overall_hits::cpu1.data 13595 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 7598 # number of overall hits
system.l2c.overall_hits::total 162654 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 28 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 17722 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 8264 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 5101 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 2487 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq misses
system.l2c.ReadReq_misses::total 174741 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8406 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3815 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 12221 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 945 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1142 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2087 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11293 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 9270 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 20563 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 17722 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 19557 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 5101 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 11757 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) misses
system.l2c.demand_misses::total 195304 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu0.inst 17722 # number of overall misses
system.l2c.overall_misses::cpu0.data 19557 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 130446 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 5101 # number of overall misses
system.l2c.overall_misses::cpu1.data 11757 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 10677 # number of overall misses
system.l2c.overall_misses::total 195304 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2541750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 428750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 1457831781 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 749814704 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 937500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 434889757 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 222071664 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 18802084724 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 7178272 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 2845410 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 10023682 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1135970 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 748476 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1884446 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1078166540 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 778316723 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1856483263 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2541750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 428750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1457831781 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 1827981244 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 937500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 434889757 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1000388387 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 20658567987 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2541750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 428750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1457831781 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 1827981244 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 937500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 434889757 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1000388387 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of overall miss cycles
system.l2c.overall_miss_latency::total 20658567987 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 215 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 94 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 50016 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 53455 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 173248 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 70 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 22249 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 14306 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 18275 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 331963 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 232253 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 232253 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 10883 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4603 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 15486 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 1194 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1203 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2397 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 14949 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 11046 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 25995 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 215 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 50016 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 68404 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173248 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 70 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 22249 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 25352 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18275 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 357958 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 215 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 50016 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 68404 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173248 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 70 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 22249 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 25352 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18275 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 357958 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.053191 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.354327 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.154597 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.028571 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.229269 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.173843 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.526387 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.772397 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828807 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.789164 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.791457 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.949293 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.870672 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.755435 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.839218 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.791037 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.053191 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.354327 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.285904 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.028571 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.229269 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.463750 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.545606 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.053191 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.354327 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.285904 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.028571 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.229269 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.463750 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.545606 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82261.131983 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 90732.660213 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85255.784552 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 89292.989144 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 107599.731740 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 853.946229 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 745.847969 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 820.201457 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1202.084656 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 655.408056 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 902.944897 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95472.110157 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83960.811543 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 90282.705004 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 105776.471485 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 105776.471485 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 1085 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 108.500000 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 103197 # number of writebacks
system.l2c.writebacks::total 103197 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 16 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 12 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 28 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 28 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 17706 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 8264 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 5089 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 2487 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 174713 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 8406 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3815 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 12221 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 945 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1142 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2087 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 11293 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 9270 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 20563 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 28 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 17706 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 19557 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 5089 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 11757 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 195276 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 28 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 17706 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 19557 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 5089 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 11757 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 195276 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 365750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1235097219 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 646670292 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 812500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 70500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370572993 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 190918836 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 16645401734 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 149850873 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 67813301 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 217664174 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16896440 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20270643 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 37167083 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 939052460 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 662623777 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1601676237 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 365750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1235097219 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 1585722752 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 812500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 70500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 370572993 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 853542613 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 18247077971 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 365750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1235097219 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1585722752 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 812500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 70500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 370572993 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 853542613 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 18247077971 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 181479250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4804405000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5954500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 824214500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5816053250 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3576332065 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 720875502 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4297207567 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8380737065 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5954500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1545090002 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 10113260817 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154597 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173843 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.526303 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772397 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828807 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.789164 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791457 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949293 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.870672 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755435 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.839218 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.791037 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.545528 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.545528 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78251.487415 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76766.721351 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 95272.828776 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17826.656317 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17775.439318 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17810.668030 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17879.830688 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17750.125219 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17808.856253 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83153.498627 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71480.450593 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 77891.175266 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 213069 # Transaction distribution
system.membus.trans_dist::ReadResp 213068 # Transaction distribution
system.membus.trans_dist::WriteReq 31079 # Transaction distribution
system.membus.trans_dist::WriteResp 31079 # Transaction distribution
system.membus.trans_dist::Writeback 139403 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 77234 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution
system.membus.trans_dist::UpgradeResp 14409 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
system.membus.trans_dist::ReadExReq 40484 # Transaction distribution
system.membus.trans_dist::ReadExResp 20462 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14202 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662750 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 784904 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 893825 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28404 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19143964 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 19335481 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 23971961 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 125081 # Total snoops (count)
system.membus.snoop_fanout::samples 510035 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 510035 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 510035 # Request fanout histogram
system.membus.reqLayer0.occupancy 81680000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 11944988 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1164089698 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1154561869 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 37506493 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 494432 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 494416 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 31079 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 31079 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 232253 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 80398 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 41961 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 122359 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50963 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50963 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1036150 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339974 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1376124 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31294456 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6755201 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 38049657 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 290334 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 898197 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.040648 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.197474 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 861687 95.94% 95.94% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36510 4.06% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 898197 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 772973190 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 636594669 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 265283017 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2748 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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