357 lines
40 KiB
Text
357 lines
40 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000026 # Number of seconds simulated
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sim_ticks 26361000 # Number of ticks simulated
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final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 148609 # Simulator instruction rate (inst/s)
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host_op_rate 184448 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 855039933 # Simulator tick rate (ticks/s)
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host_mem_usage 228200 # Number of bytes of host memory used
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host_seconds 0.03 # Real time elapsed on the host
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sim_insts 4574 # Number of instructions simulated
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sim_ops 5682 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 22400 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 350 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 849740146 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 546261523 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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system.cpu.numCycles 52722 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 4574 # Number of instructions committed
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system.cpu.committedOps 5682 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 185 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
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system.cpu.num_int_insts 4985 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 28701 # number of times the integer registers were read
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system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 2139 # number of memory refs
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system.cpu.num_load_insts 1201 # Number of load instructions
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system.cpu.num_store_insts 938 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 52722 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 1 # number of replacements
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system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use
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system.cpu.icache.total_refs 4373 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits
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system.cpu.icache.overall_hits::total 4373 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
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system.cpu.icache.overall_misses::total 241 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits
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system.cpu.dcache.overall_hits::total 1919 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
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system.cpu.dcache.overall_misses::total 141 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 32 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 350 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|