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gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
Nilay Vaish 247e4e9ab4 stats: updates due to changes to ruby 
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
2013-06-10 06:46:20 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.202255 # Number of seconds simulated
sim_ticks 202254809500 # Number of ticks simulated
final_tick 202254809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 148306 # Simulator instruction rate (inst/s)
host_op_rate 167206 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 59369383 # Simulator tick rate (ticks/s)
host_mem_usage 288744 # Number of bytes of host memory used
host_seconds 3406.72 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 569624283 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 216064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9266496 # Number of bytes read from this memory
system.physmem.bytes_read::total 9482560 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 216064 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 216064 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6247616 # Number of bytes written to this memory
system.physmem.bytes_written::total 6247616 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3376 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 144789 # Number of read requests responded to by this memory
system.physmem.num_reads::total 148165 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 97619 # Number of write requests responded to by this memory
system.physmem.num_writes::total 97619 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1068276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 45815949 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 46884225 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1068276 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1068276 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 30889827 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 30889827 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 30889827 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1068276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 45815949 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 77774052 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 148166 # Total number of read requests seen
system.physmem.writeReqs 97619 # Total number of write requests seen
system.physmem.cpureqs 245800 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 9482560 # Total number of bytes read from memory
system.physmem.bytesWritten 6247616 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 9482560 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6247616 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 82 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 10 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 9642 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 9223 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 9266 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 8974 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 9810 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 9620 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 9110 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 8299 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 8798 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 8898 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 8934 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 9719 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 9635 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 9761 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 8951 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 9444 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 6285 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 5883 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 6272 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 6268 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 5542 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 5814 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 5893 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 5986 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6510 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 6368 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 6328 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 6050 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6141 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry
system.physmem.totGap 202254789500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 148166 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 97619 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 138581 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 8939 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 502 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 56237 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 279.600690 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 133.370876 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 689.275557 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 28174 50.10% 50.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 10389 18.47% 68.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 4755 8.46% 77.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 2751 4.89% 81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 1840 3.27% 85.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 1148 2.04% 87.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 864 1.54% 88.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 636 1.13% 89.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 440 0.78% 90.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 367 0.65% 91.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 311 0.55% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 257 0.46% 92.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 204 0.36% 92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 168 0.30% 93.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 168 0.30% 93.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 154 0.27% 93.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 160 0.28% 94.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 140 0.25% 94.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 187 0.33% 95.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 266 0.47% 95.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 973 1.73% 97.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 245 0.44% 97.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 154 0.27% 97.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 175 0.31% 98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 98 0.17% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 108 0.19% 98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 69 0.12% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 37 0.07% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 38 0.07% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 29 0.05% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 23 0.04% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 13 0.02% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 16 0.03% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 14 0.02% 99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 7 0.01% 99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 15 0.03% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 12 0.02% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 9 0.02% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 15 0.03% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 6 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 12 0.02% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 9 0.02% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 5 0.01% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 6 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 8 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 3 0.01% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 4 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 3 0.01% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 2 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 3 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 4 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 2 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 257 0.46% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 56237 # Bytes accessed per row activation
system.physmem.totQLat 1508178750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 4631350000 # Sum of mem lat for all requests
system.physmem.totBusLat 740420000 # Total cycles spent in databus access
system.physmem.totBankLat 2382751250 # Total cycles spent in bank access
system.physmem.avgQLat 10184.62 # Average queueing delay per request
system.physmem.avgBankLat 16090.54 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 31275.15 # Average memory access latency
system.physmem.avgRdBW 46.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 46.88 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.61 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
system.physmem.avgWrQLen 8.03 # Average write queue length over time
system.physmem.readRowHits 130565 # Number of row buffer hits during reads
system.physmem.writeRowHits 58894 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.17 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 60.33 # Row buffer hit rate for writes
system.physmem.avgGap 822893.14 # Average gap between requests
system.membus.throughput 77774052 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 46889 # Transaction distribution
system.membus.trans_dist::ReadResp 46888 # Transaction distribution
system.membus.trans_dist::Writeback 97619 # Transaction distribution
system.membus.trans_dist::UpgradeReq 10 # Transaction distribution
system.membus.trans_dist::UpgradeResp 10 # Transaction distribution
system.membus.trans_dist::ReadExReq 101277 # Transaction distribution
system.membus.trans_dist::ReadExResp 101277 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 393970 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 393970 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15730176 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 15730176 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 15730176 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1080021750 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 1400430490 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu.branchPred.lookups 182798066 # Number of BP lookups
system.cpu.branchPred.condPredicted 143118312 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 7265128 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 93487974 # Number of BTB lookups
system.cpu.branchPred.BTBHits 87210419 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 93.285174 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 12673306 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 115887 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 404509620 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 119370691 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 761605740 # Number of instructions fetch has processed
system.cpu.fetch.Branches 182798066 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 99883725 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 170135363 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 35678308 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 77091190 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 114522071 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2438323 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 394207776 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.166768 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.987550 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 224085033 56.84% 56.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 14184034 3.60% 60.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 22893795 5.81% 66.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 22742785 5.77% 72.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 20889438 5.30% 77.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 11596058 2.94% 80.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 13058827 3.31% 83.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 11996655 3.04% 86.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 52761151 13.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 394207776 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.451900 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.882788 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 129058894 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 72583383 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 158800998 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 6228602 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 27535899 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 26119356 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 76952 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 825527591 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 297029 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 27535899 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 135653385 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 10117573 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 47448086 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 158253744 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 15199089 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 800585743 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1337 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 3048778 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 8951135 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 327 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 954274745 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3500443085 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3500441750 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1335 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 288022454 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2292887 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2292884 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 41810314 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 170245714 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 73473402 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 28600787 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 15864837 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 755023538 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3775253 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 665282495 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1376367 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 187359932 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 479861351 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 797621 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 394207776 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.687644 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.734895 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 138685304 35.18% 35.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 69974148 17.75% 52.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 71487489 18.13% 71.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 53410155 13.55% 84.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 31169458 7.91% 92.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15996787 4.06% 96.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8767931 2.22% 98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2898481 0.74% 99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1818023 0.46% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 394207776 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 480591 5.01% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 6540572 68.21% 73.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2567937 26.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 447761903 67.30% 67.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 383485 0.06% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 153367544 23.05% 90.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 63769466 9.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 665282495 # Type of FU issued
system.cpu.iq.rate 1.644664 # Inst issue rate
system.cpu.iq.fu_busy_cnt 9589100 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.014414 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1735738010 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 946965616 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 646015342 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 674871482 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 8586210 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 44216159 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 41012 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 810921 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 16612925 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6939 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 27535899 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 5281663 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 386285 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 760357745 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1115007 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 170245714 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 73473402 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2286711 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 219038 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 12304 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 810921 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4337552 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4003513 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8341065 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 655860831 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 150086003 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 9421664 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1558954 # number of nop insts executed
system.cpu.iew.exec_refs 212560295 # number of memory reference insts executed
system.cpu.iew.exec_branches 138490949 # Number of branches executed
system.cpu.iew.exec_stores 62474292 # Number of stores executed
system.cpu.iew.exec_rate 1.621373 # Inst execution rate
system.cpu.iew.wb_sent 650984327 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 646015358 # cumulative count of insts written-back
system.cpu.iew.wb_producers 374693412 # num instructions producing a value
system.cpu.iew.wb_consumers 646299598 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.597033 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.579752 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 189415917 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 7190999 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 366671877 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.557164 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.230606 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 158948889 43.35% 43.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 98517703 26.87% 70.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 33831327 9.23% 79.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 18775088 5.12% 84.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 16222583 4.42% 88.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7456199 2.03% 91.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 6938304 1.89% 92.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3192877 0.87% 93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 22788907 6.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 366671877 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 182890032 # Number of memory references committed
system.cpu.commit.loads 126029555 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.branches 121548301 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.bw_lim_events 22788907 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1104259916 # The number of ROB reads
system.cpu.rob.rob_writes 1548425259 # The number of ROB writes
system.cpu.timesIdled 328032 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 10301844 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
system.cpu.cpi 0.800632 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.800632 # CPI: Total CPI of All Threads
system.cpu.ipc 1.249013 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.249013 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3058504664 # number of integer regfile reads
system.cpu.int_regfile_writes 751970917 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 210811449 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
system.cpu.toL2Bus.throughput 735317990 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 864350 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 864349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1110574 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 348852 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 348852 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33690 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503354 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 3537044 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1075520 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147641024 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 148716544 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 148716544 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2272504241 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 25334982 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1794529465 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.replacements 14954 # number of replacements
system.cpu.icache.tagsinuse 1101.424981 # Cycle average of tags in use
system.cpu.icache.total_refs 114501007 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 16812 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 6810.671366 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1101.424981 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.537805 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.537805 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 114501007 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 114501007 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 114501007 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 114501007 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 114501007 # number of overall hits
system.cpu.icache.overall_hits::total 114501007 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 21063 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 21063 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 21063 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 21063 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 21063 # number of overall misses
system.cpu.icache.overall_misses::total 21063 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 592520500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 592520500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 592520500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 592520500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 592520500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 592520500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 114522070 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 114522070 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 114522070 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 114522070 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 114522070 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 114522070 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28130.869297 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28130.869297 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28130.869297 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28130.869297 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 770 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 64.166667 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4178 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 4178 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 4178 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 4178 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 4178 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 4178 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16885 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 16885 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 16885 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 16885 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 16885 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 16885 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427572518 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 427572518 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427572518 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 427572518 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427572518 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 427572518 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000147 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000147 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000147 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25322.624696 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25322.624696 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 115420 # number of replacements
system.cpu.l2cache.tagsinuse 27103.497670 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1780537 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 146672 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 12.139584 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 102160649500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 23017.556020 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 361.817862 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 3724.123788 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.702440 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.011042 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.113651 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.827133 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 13425 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 803929 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 817354 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1110574 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1110574 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 63 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 63 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 13425 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1051504 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1064929 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 13425 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1051504 # number of overall hits
system.cpu.l2cache.overall_hits::total 1064929 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3381 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 43536 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 46917 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 101277 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 101277 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3381 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 144813 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 148194 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3381 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 144813 # number of overall misses
system.cpu.l2cache.overall_misses::total 148194 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 276063000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3642504500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3918567500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7048588500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7048588500 # number of ReadExReq miss cycles
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system.cpu.l2cache.Writeback_accesses::writebacks 1110574 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1110574 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83666.494395 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69597.129654 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69597.129654 # average ReadExReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81651.286602 # average overall miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 97619 # number of writebacks
system.cpu.l2cache.writebacks::total 97619 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
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system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
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system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3377 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43512 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 46889 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 101277 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::total 148166 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 233867750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8886477250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9120345000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 233867750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8886477250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9120345000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054253 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136986 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136986 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290315 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290315 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.122136 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.122136 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69253.109269 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71270.821842 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71125.503850 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57123.939789 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57123.939789 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1192221 # number of replacements
system.cpu.dcache.tagsinuse 4057.785515 # Cycle average of tags in use
system.cpu.dcache.total_refs 190145872 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1196317 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 158.942715 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4057.785515 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.990670 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 136179358 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 136179358 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 50988931 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 50988931 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488837 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488837 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 187168289 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 187168289 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 187168289 # number of overall hits
system.cpu.dcache.overall_hits::total 187168289 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1699578 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1699578 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3250375 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3250375 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 4949953 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4949953 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4949953 # number of overall misses
system.cpu.dcache.overall_misses::total 4949953 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29584540500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 29584540500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 69108485945 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 69108485945 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 701500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 701500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 98693026445 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 98693026445 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 98693026445 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 98693026445 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 137878936 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 137878936 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488874 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488874 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 192118242 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 192118242 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 192118242 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 192118242 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012327 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012327 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059927 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.059927 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025765 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025765 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025765 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.025765 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17406.991912 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17406.991912 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21261.696249 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 21261.696249 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18959.459459 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18959.459459 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19938.174452 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19938.174452 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 19233 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 40481 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1722 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 665 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.168990 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 60.873684 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1110574 # number of writebacks
system.cpu.dcache.writebacks::total 1110574 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851549 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 851549 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902014 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2902014 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3753563 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3753563 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3753563 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3753563 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848029 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 848029 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348361 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 348361 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1196390 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1196390 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1196390 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1196390 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12568519034 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12568519034 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9922118995 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9922118995 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22490638029 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 22490638029 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22490638029 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 22490638029 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14820.859940 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14820.859940 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28482.289909 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28482.289909 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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