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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

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---------- Begin Simulation Statistics ----------
sim_seconds 1.960910 # Number of seconds simulated
sim_ticks 1960909874500 # Number of ticks simulated
final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1305982 # Simulator instruction rate (inst/s)
host_op_rate 1305981 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42027651646 # Simulator tick rate (ticks/s)
host_mem_usage 309852 # Number of bytes of host memory used
host_seconds 46.66 # Real time elapsed on the host
sim_insts 60933947 # Number of instructions simulated
sim_ops 60933947 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory
system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory
system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory
system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory
system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 449082 # Number of read requests accepted
system.physmem.writeReqs 120995 # Number of write requests accepted
system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue
system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 28167 # Per bank write bursts
system.physmem.perBankRdBursts::1 28459 # Per bank write bursts
system.physmem.perBankRdBursts::2 28057 # Per bank write bursts
system.physmem.perBankRdBursts::3 27664 # Per bank write bursts
system.physmem.perBankRdBursts::4 27762 # Per bank write bursts
system.physmem.perBankRdBursts::5 27793 # Per bank write bursts
system.physmem.perBankRdBursts::6 28259 # Per bank write bursts
system.physmem.perBankRdBursts::7 27872 # Per bank write bursts
system.physmem.perBankRdBursts::8 28083 # Per bank write bursts
system.physmem.perBankRdBursts::9 27730 # Per bank write bursts
system.physmem.perBankRdBursts::10 27672 # Per bank write bursts
system.physmem.perBankRdBursts::11 28135 # Per bank write bursts
system.physmem.perBankRdBursts::12 28179 # Per bank write bursts
system.physmem.perBankRdBursts::13 28505 # Per bank write bursts
system.physmem.perBankRdBursts::14 28654 # Per bank write bursts
system.physmem.perBankRdBursts::15 28035 # Per bank write bursts
system.physmem.perBankWrBursts::0 7928 # Per bank write bursts
system.physmem.perBankWrBursts::1 7868 # Per bank write bursts
system.physmem.perBankWrBursts::2 7543 # Per bank write bursts
system.physmem.perBankWrBursts::3 7157 # Per bank write bursts
system.physmem.perBankWrBursts::4 7275 # Per bank write bursts
system.physmem.perBankWrBursts::5 7314 # Per bank write bursts
system.physmem.perBankWrBursts::6 7747 # Per bank write bursts
system.physmem.perBankWrBursts::7 7251 # Per bank write bursts
system.physmem.perBankWrBursts::8 7322 # Per bank write bursts
system.physmem.perBankWrBursts::9 7110 # Per bank write bursts
system.physmem.perBankWrBursts::10 7099 # Per bank write bursts
system.physmem.perBankWrBursts::11 7523 # Per bank write bursts
system.physmem.perBankWrBursts::12 7681 # Per bank write bursts
system.physmem.perBankWrBursts::13 8141 # Per bank write bursts
system.physmem.perBankWrBursts::14 8335 # Per bank write bursts
system.physmem.perBankWrBursts::15 7684 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 1960902862500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 449082 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 120995 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 64 0.13% 90.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 84 0.17% 90.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 51 0.10% 90.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 54 0.11% 91.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 70 0.14% 91.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 45 0.09% 91.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 72 0.15% 91.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 49 0.10% 91.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 40 0.08% 91.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 72 0.15% 91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 42 0.09% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 45 0.09% 91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 69 0.14% 92.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 44 0.09% 92.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 64 0.13% 92.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 43 0.09% 92.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 76 0.15% 92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 39 0.08% 92.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 46 0.09% 92.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 67 0.14% 92.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 46 0.09% 93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 66 0.13% 93.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 46 0.09% 93.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 37 0.07% 93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 72 0.15% 93.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 38 0.08% 93.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 42 0.09% 93.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 69 0.14% 93.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 43 0.09% 93.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 64 0.13% 94.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 42 0.09% 94.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 41 0.08% 94.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 74 0.15% 94.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 37 0.07% 94.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 43 0.09% 94.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291 66 0.13% 94.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 46 0.09% 94.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 64 0.13% 94.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 43 0.09% 94.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 37 0.07% 95.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 404 0.82% 95.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 34 0.07% 95.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 44 0.09% 96.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803 36 0.07% 96.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 44 0.09% 96.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 34 0.07% 96.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 44 0.09% 96.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 33 0.07% 96.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 41 0.08% 96.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 51 0.10% 96.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 44 0.09% 96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 32 0.06% 96.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 40 0.08% 96.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443 37 0.07% 96.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 43 0.09% 96.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571 35 0.07% 97.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635 40 0.08% 97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699 33 0.07% 97.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 47 0.10% 97.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827 34 0.07% 97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 43 0.09% 97.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955 35 0.07% 97.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 44 0.09% 97.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083 34 0.07% 97.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 44 0.09% 97.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211 38 0.08% 97.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 42 0.09% 97.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339 35 0.07% 97.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 43 0.09% 98.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467 32 0.06% 98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 40 0.08% 98.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595 37 0.07% 98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 41 0.08% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 32 0.06% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 431 0.87% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 10 0.02% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619 3 0.01% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523 2 0.00% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12291 2 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12355 3 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675 3 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation
system.physmem.totQLat 6346588750 # Total ticks spent queuing
system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers
system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks
system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing
system.physmem.readRowHits 424775 # Number of row buffer hits during reads
system.physmem.writeRowHits 95849 # Number of row buffer hits during writes
system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes
system.physmem.avgGap 3439715.80 # Average gap between requests
system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 18666756 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 292805 # Transaction distribution
system.membus.trans_dist::ReadResp 292805 # Transaction distribution
system.membus.trans_dist::WriteReq 14109 # Transaction distribution
system.membus.trans_dist::WriteResp 14109 # Transaction distribution
system.membus.trans_dist::Writeback 120995 # Transaction distribution
system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution
system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution
system.membus.trans_dist::ReadExReq 164894 # Transaction distribution
system.membus.trans_dist::ReadExResp 164048 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36567218 # Total data (bytes)
system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 342160 # number of replacements
system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use
system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 761 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5186 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7242 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 51881 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 25932224 # Number of tag accesses
system.l2c.tags.data_accesses 25932224 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits
system.l2c.Writeback_hits::total 791641 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 129054 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 42974 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 172028 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 684719 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 793579 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 317383 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 150404 # number of demand (read+write) hits
system.l2c.demand_hits::total 1946085 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 684719 # number of overall hits
system.l2c.overall_hits::cpu0.data 793579 # number of overall hits
system.l2c.overall_hits::cpu1.inst 317383 # number of overall hits
system.l2c.overall_hits::cpu1.data 150404 # number of overall hits
system.l2c.overall_hits::total 1946085 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 13026 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 271672 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285443 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1793 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 4742 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 117950 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 5055 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 123005 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 13026 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 389622 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 5297 # number of demand (read+write) misses
system.l2c.demand_misses::total 408448 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 13026 # number of overall misses
system.l2c.overall_misses::cpu0.data 389622 # number of overall misses
system.l2c.overall_misses::cpu1.inst 503 # number of overall misses
system.l2c.overall_misses::cpu1.data 5297 # number of overall misses
system.l2c.overall_misses::total 408448 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 997409492 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 17552881248 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 35450000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 19470500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 18605211240 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1291954 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 10252557 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 11544511 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 835964 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 163493 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 999457 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 8264985252 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 387201489 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 8652186741 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 997409492 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 25817866500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 35450000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 406671989 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 27257397981 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 997409492 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 25817866500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 35450000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 406671989 # number of overall miss cycles
system.l2c.overall_miss_latency::total 27257397981 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 697745 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 936197 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 317886 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 107672 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2059500 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 791641 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 791641 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 3129 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 2332 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 957 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 948 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1905 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 247004 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 48029 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 295033 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 697745 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1183201 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 317886 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 155701 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2354533 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 697745 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1183201 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 317886 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 155701 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2354533 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.018669 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.290187 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.001582 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.002248 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.138598 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942474 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768868 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.868339 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.960293 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.977848 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.969029 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.477523 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.105249 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.416919 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.018669 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.329295 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.001582 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.034020 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.173473 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.018669 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.329295 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.001582 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.034020 # miss rate for overall accesses
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system.l2c.UpgradeReq_mshr_miss_rate::total 0.868339 # mshr miss rate for UpgradeReq accesses
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
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system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles
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system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 7532654 # DTB read hits
system.cpu0.dtb.read_misses 7812 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
system.cpu0.dtb.read_accesses 524694 # DTB read accesses
system.cpu0.dtb.write_hits 5120278 # DTB write hits
system.cpu0.dtb.write_misses 919 # DTB write misses
system.cpu0.dtb.write_acv 139 # DTB write access violations
system.cpu0.dtb.write_accesses 202960 # DTB write accesses
system.cpu0.dtb.data_hits 12652932 # DTB hits
system.cpu0.dtb.data_misses 8731 # DTB misses
system.cpu0.dtb.data_acv 349 # DTB access violations
system.cpu0.dtb.data_accesses 727654 # DTB accesses
system.cpu0.itb.fetch_hits 3655515 # ITB hits
system.cpu0.itb.fetch_misses 4023 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
system.cpu0.itb.fetch_accesses 3659538 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 3921819749 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 47983654 # Number of instructions committed
system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses
system.cpu0.num_func_calls 1203620 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls
system.cpu0.num_int_insts 44515044 # number of integer instructions
system.cpu0.num_fp_insts 211401 # number of float instructions
system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read
system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written
system.cpu0.num_mem_refs 12694028 # number of memory refs
system.cpu0.num_load_insts 7560495 # Number of load instructions
system.cpu0.num_store_insts 5133533 # Number of store instructions
system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles
system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles
system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 234 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed
system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed
system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed
system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 149515 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1377
system.cpu0.kern.mode_good::user 1378
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3091 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.throughput 103937669 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 201437426 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 1399302 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
system.iobus.trans_dist::WriteReq 55661 # Transaction distribution
system.iobus.trans_dist::WriteResp 55661 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2743906 # Total data (bytes)
system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 697136 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 48690501 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 48690501 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits
system.cpu0.icache.overall_hits::total 47294969 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses
system.cpu0.icache.overall_misses::total 697766 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697766 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 697766 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 697766 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 697766 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 697766 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 697766 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8583721995 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 8583721995 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8583721995 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 8583721995 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8583721995 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 8583721995 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1186229 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986859 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.986859 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 51851796 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51851796 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 148003 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11158591 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11158591 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11158591 # number of overall hits
system.cpu0.dcache.overall_hits::total 11158591 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 939483 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 939483 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 256736 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 256736 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13633 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13633 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5600 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5600 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1196219 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1196219 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1196219 # number of overall misses
system.cpu0.dcache.overall_misses::total 1196219 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27076055500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 27076055500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10459807694 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 10459807694 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148332750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 148332750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43345419 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 43345419 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 37535863194 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 37535863194 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 37535863194 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 37535863194 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7391218 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7391218 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4963592 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4963592 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154145 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 154145 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153603 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 153603 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12354810 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12354810 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12354810 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12354810 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127108 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.127108 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051724 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.051724 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088443 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088443 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036458 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036458 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096822 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.096822 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096822 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.096822 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10880.418837 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10880.418837 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7740.253393 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7740.253393 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 31378.755223 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31378.755223 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks
system.cpu0.dcache.writebacks::total 682519 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 2383442 # DTB read hits
system.cpu1.dtb.read_misses 2620 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 205337 # DTB read accesses
system.cpu1.dtb.write_hits 1706844 # DTB write hits
system.cpu1.dtb.write_misses 235 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
system.cpu1.dtb.write_accesses 89739 # DTB write accesses
system.cpu1.dtb.data_hits 4090286 # DTB hits
system.cpu1.dtb.data_misses 2855 # DTB misses
system.cpu1.dtb.data_acv 24 # DTB access violations
system.cpu1.dtb.data_accesses 295076 # DTB accesses
system.cpu1.itb.fetch_hits 1814139 # ITB hits
system.cpu1.itb.fetch_misses 1064 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
system.cpu1.itb.fetch_accesses 1815203 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 3919927793 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 12950293 # Number of instructions committed
system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses
system.cpu1.num_func_calls 410658 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls
system.cpu1.num_int_insts 11929999 # number of integer instructions
system.cpu1.num_fp_insts 174217 # number of float instructions
system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read
system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written
system.cpu1.num_mem_refs 4113222 # number of memory refs
system.cpu1.num_load_insts 2397194 # Number of load instructions
system.cpu1.num_store_insts 1716028 # Number of store instructions
system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles
system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 92 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed
system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed
system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed
system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed
system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 71838 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches
system.cpu1.kern.mode_switch::user 368 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 809
system.cpu1.kern.mode_good::user 368
system.cpu1.kern.mode_good::idle 441
system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 2002 # number of times the context was actually changed
system.cpu1.icache.tags.replacements 317336 # number of replacements
system.cpu1.icache.tags.tagsinuse 446.450379 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 12635285 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 317847 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 39.752727 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1958987590000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 13271059 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 13271059 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 12635285 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 12635285 # number of overall hits
system.cpu1.icache.overall_hits::total 12635285 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 317887 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 317887 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 317887 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 317887 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 317887 # number of overall misses
system.cpu1.icache.overall_misses::total 317887 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4180819492 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4180819492 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4180819492 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4180819492 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4180819492 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4180819492 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953172 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 12953172 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 12953172 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 12953172 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 12953172 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 12953172 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024541 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.024541 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024541 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.024541 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024541 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.024541 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13151.904582 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13151.904582 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317887 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 317887 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 317887 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 317887 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 317887 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 317887 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3544847508 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3544847508 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3544847508 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3544847508 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3544847508 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3544847508 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024541 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.024541 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.024541 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 158764 # number of replacements
system.cpu1.dcache.tags.tagsinuse 485.752776 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 3916687 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 159090 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 24.619316 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 16587420 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 16587420 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2220669 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1595283 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1595283 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48031 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 48031 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50613 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 50613 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3815952 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3815952 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3815952 # number of overall hits
system.cpu1.dcache.overall_hits::total 3815952 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 116704 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 116704 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 56889 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 56889 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9081 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 9081 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6019 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 6019 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 173593 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 173593 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 173593 # number of overall misses
system.cpu1.dcache.overall_misses::total 173593 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411486000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 1411486000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1044020804 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 1044020804 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82357000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 82357000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44184927 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 44184927 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 2455506804 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 2455506804 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 2455506804 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 2455506804 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2337373 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2337373 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1652172 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1652172 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57112 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 57112 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56632 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 56632 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3989545 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3989545 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3989545 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 3989545 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049930 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.049930 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034433 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.034433 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159003 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159003 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106283 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106283 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043512 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.043512 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043512 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.043512 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9069.155379 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9069.155379 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7340.908290 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7340.908290 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks
system.cpu1.dcache.writebacks::total 109122 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6019 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 6019 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 173593 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 173593 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 173593 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 173593 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1178000000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1178000000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 927938196 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 927938196 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64195000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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