1090 lines
123 KiB
Text
1090 lines
123 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.533762 # Number of seconds simulated
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sim_ticks 533761922000 # Number of ticks simulated
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final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 155948 # Simulator instruction rate (inst/s)
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host_op_rate 173972 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 53891847 # Simulator tick rate (ticks/s)
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host_mem_usage 269768 # Number of bytes of host memory used
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host_seconds 9904.32 # Real time elapsed on the host
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sim_insts 1544563023 # Number of instructions simulated
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sim_ops 1723073835 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory
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system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory
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system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 2246694 # Number of read requests accepted
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system.physmem.writeReqs 1100579 # Number of write requests accepted
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system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue
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system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 139629 # Per bank write bursts
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system.physmem.perBankRdBursts::1 136292 # Per bank write bursts
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system.physmem.perBankRdBursts::2 133828 # Per bank write bursts
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system.physmem.perBankRdBursts::3 136435 # Per bank write bursts
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system.physmem.perBankRdBursts::4 134766 # Per bank write bursts
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system.physmem.perBankRdBursts::5 135151 # Per bank write bursts
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system.physmem.perBankRdBursts::6 136244 # Per bank write bursts
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system.physmem.perBankRdBursts::7 136309 # Per bank write bursts
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system.physmem.perBankRdBursts::8 143829 # Per bank write bursts
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system.physmem.perBankRdBursts::9 146501 # Per bank write bursts
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system.physmem.perBankRdBursts::10 144298 # Per bank write bursts
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system.physmem.perBankRdBursts::11 146295 # Per bank write bursts
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system.physmem.perBankRdBursts::12 145712 # Per bank write bursts
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system.physmem.perBankRdBursts::13 146106 # Per bank write bursts
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system.physmem.perBankRdBursts::14 142241 # Per bank write bursts
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system.physmem.perBankRdBursts::15 142471 # Per bank write bursts
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system.physmem.perBankWrBursts::0 69077 # Per bank write bursts
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system.physmem.perBankWrBursts::1 67426 # Per bank write bursts
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system.physmem.perBankWrBursts::2 65726 # Per bank write bursts
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system.physmem.perBankWrBursts::3 66343 # Per bank write bursts
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system.physmem.perBankWrBursts::4 66130 # Per bank write bursts
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system.physmem.perBankWrBursts::5 66357 # Per bank write bursts
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system.physmem.perBankWrBursts::6 67984 # Per bank write bursts
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system.physmem.perBankWrBursts::7 68878 # Per bank write bursts
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system.physmem.perBankWrBursts::8 70373 # Per bank write bursts
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system.physmem.perBankWrBursts::9 70997 # Per bank write bursts
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system.physmem.perBankWrBursts::10 70493 # Per bank write bursts
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system.physmem.perBankWrBursts::11 70981 # Per bank write bursts
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system.physmem.perBankWrBursts::12 70269 # Per bank write bursts
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system.physmem.perBankWrBursts::13 70812 # Per bank write bursts
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system.physmem.perBankWrBursts::14 69646 # Per bank write bursts
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system.physmem.perBankWrBursts::15 69069 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
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system.physmem.totGap 533761847000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 2246694 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1100579 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 2078319 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 103.049035 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 79.954808 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 184.695982 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 1660986 79.92% 79.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 227336 10.94% 90.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 68882 3.31% 94.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 37662 1.81% 95.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 25035 1.20% 97.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 12093 0.58% 97.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 8438 0.41% 98.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 8141 0.39% 98.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 4391 0.21% 98.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 3442 0.17% 98.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-705 2829 0.14% 99.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-769 1974 0.09% 99.18% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::832-833 1676 0.08% 99.26% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::896-897 1442 0.07% 99.33% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::960-961 1174 0.06% 99.38% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1024-1025 1106 0.05% 99.44% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1088-1089 969 0.05% 99.48% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1152-1153 858 0.04% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1217 735 0.04% 99.56% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1280-1281 673 0.03% 99.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1345 651 0.03% 99.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1409 3128 0.15% 99.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1473 421 0.02% 99.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1537 240 0.01% 99.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1601 179 0.01% 99.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1665 200 0.01% 99.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1729 207 0.01% 99.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1793 498 0.02% 99.86% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1985 136 0.01% 99.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2049 128 0.01% 99.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2113 89 0.00% 99.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2177 121 0.01% 99.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2241 102 0.00% 99.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2305 117 0.01% 99.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2369 77 0.00% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2433 74 0.00% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2497 59 0.00% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2561 70 0.00% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2625 60 0.00% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2689 54 0.00% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2753 55 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2817 76 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2881 49 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2945 45 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3009 33 0.00% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3073 66 0.00% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3137 39 0.00% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3201 33 0.00% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3265 36 0.00% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3329 47 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3393 27 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3521 22 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3585 27 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3649 21 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3713 25 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3841 40 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4033 16 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4097 30 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4161 10 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4225 21 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4289 16 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4353 36 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4417 15 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4737 17 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4801 17 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4865 32 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4929 10 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5057 15 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5121 31 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5249 10 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5313 9 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5377 206 0.01% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation
|
|
system.physmem.totQLat 32815970750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks
|
|
system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 3.13 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 932061 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 336288 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 159461.70 # Average gap between requests
|
|
system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.membus.throughput 401350114 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 1420099 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1420098 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1100579 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 826595 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 826595 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 214225408 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 4.0 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 303426723 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
|
system.cpu.numCycles 1067523845 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 542 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued
|
|
system.cpu.iq.rate 1.891055 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 143 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 238318975 # Number of branches executed
|
|
system.cpu.iew.exec_stores 190166415 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.862270 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1295394361 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 660773814 # Number of memory references committed
|
|
system.cpu.commit.loads 485926769 # Number of loads committed
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
system.cpu.commit.branches 213462426 # Number of branches committed
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 2995284619 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4474886700 # The number of ROB writes
|
|
system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 98 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 94 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 19 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 289577640 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1205 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 430 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55854002 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 55854002 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55854002 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 55854002 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55854002 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 55854002 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72069.680000 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72069.680000 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 2214011 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31532.870200 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 9247003 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 2243785 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.121163 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14303.376165 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.256077 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 17209.237958 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.436504 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.525184 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.962307 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1894 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23751 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3958 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908630 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 111217422 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 111217422 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6289318 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6289347 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3782070 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3782070 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1066898 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1066898 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7356216 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7356245 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7356216 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7356245 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 746 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1419362 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1420108 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 826595 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 826595 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 746 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2245957 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 2246703 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 746 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2245957 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 2246703 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 54783500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125692113250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 125746896750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76318094500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 76318094500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 54783500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 202010207750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 202064991250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 54783500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 202010207750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 202064991250 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7708680 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7709455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3782070 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3782070 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893493 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1893493 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9602173 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9602948 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9602173 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9602948 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962581 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184125 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.184203 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436545 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436545 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962581 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.233901 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.233960 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962581 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.233901 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.233960 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73436.327078 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88555.360260 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 88547.418048 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92328.279871 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92328.279871 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.327078 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89943.933811 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 89938.452590 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.327078 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89943.933811 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 89938.452590 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1100579 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1100579 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419355 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1420099 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826595 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 826595 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2245950 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 2246694 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2245950 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 2246694 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45263000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107889512500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107934775500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65933341000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65933341000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45263000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173822853500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 173868116500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45263000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173822853500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 173868116500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184124 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184202 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436545 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436545 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.233959 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.233959 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60837.365591 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76013.056987 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76005.106334 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79764.988900 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79764.988900 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 9598076 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4088.041397 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 656012597 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9602172 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 68.319188 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041397 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 656012474 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 11506498 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 11506498 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5629782 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5629782 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 17136280 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 17136280 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 17136280 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 17136280 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 363307841237 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 363307841237 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 307618244019 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 307618244019 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 670926085256 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3782070 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|