1156 lines
131 KiB
Plaintext
1156 lines
131 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000026 # Number of seconds simulated
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sim_ticks 25607000 # Number of ticks simulated
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final_tick 25607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 110915 # Simulator instruction rate (inst/s)
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host_op_rate 110902 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 222369986 # Simulator tick rate (ticks/s)
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host_mem_usage 254744 # Number of bytes of host memory used
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host_seconds 0.12 # Real time elapsed on the host
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sim_insts 12770 # Number of instructions simulated
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sim_ops 12770 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory
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system.physmem.bytes_read::total 61760 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 341 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 965 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1559573554 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 852266958 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2411840512 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1559573554 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1559573554 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1559573554 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 852266958 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2411840512 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 966 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 966 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 61824 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 61824 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 84 # Per bank write bursts
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system.physmem.perBankRdBursts::1 150 # Per bank write bursts
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system.physmem.perBankRdBursts::2 77 # Per bank write bursts
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system.physmem.perBankRdBursts::3 58 # Per bank write bursts
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system.physmem.perBankRdBursts::4 90 # Per bank write bursts
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system.physmem.perBankRdBursts::5 46 # Per bank write bursts
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system.physmem.perBankRdBursts::6 32 # Per bank write bursts
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system.physmem.perBankRdBursts::7 50 # Per bank write bursts
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system.physmem.perBankRdBursts::8 41 # Per bank write bursts
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system.physmem.perBankRdBursts::9 37 # Per bank write bursts
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system.physmem.perBankRdBursts::10 28 # Per bank write bursts
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system.physmem.perBankRdBursts::11 34 # Per bank write bursts
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system.physmem.perBankRdBursts::12 15 # Per bank write bursts
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system.physmem.perBankRdBursts::13 120 # Per bank write bursts
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system.physmem.perBankRdBursts::14 67 # Per bank write bursts
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system.physmem.perBankRdBursts::15 37 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 25577000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 966 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 323 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 171 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 278.748815 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 172.887192 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 291.495109 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 76 36.02% 36.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 57 27.01% 63.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 23 10.90% 73.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 12 5.69% 79.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 8 3.79% 83.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 11 5.21% 88.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 6 2.84% 91.47% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 6 2.84% 94.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 12 5.69% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation
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system.physmem.totQLat 14120500 # Total ticks spent queuing
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system.physmem.totMemAccLat 32233000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 4830000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 14617.49 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 33367.49 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 2414.34 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 2414.34 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 18.86 # Data bus utilization in percentage
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system.physmem.busUtilRead 18.86 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 745 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 26477.23 # Average gap between requests
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system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 4477200 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 23482530 # Total energy per rank (pJ)
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system.physmem_0.averagePower 994.232548 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 763000 # Time in different power states
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system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 2628600 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 15488325 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 585000 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 21314310 # Total energy per rank (pJ)
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system.physmem_1.averagePower 902.431754 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 878500 # Time in different power states
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system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 21974000 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
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system.cpu.branchPred.lookups 4896 # Number of BP lookups
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system.cpu.branchPred.condPredicted 2917 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 793 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 3827 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 1151 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 30.075777 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 688 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 51 # Number of incorrect RAS predictions.
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system.cpu.branchPred.indirectLookups 820 # Number of indirect predictor lookups.
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system.cpu.branchPred.indirectHits 149 # Number of indirect target hits.
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system.cpu.branchPred.indirectMisses 671 # Number of indirect misses.
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system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 4131 # DTB read hits
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system.cpu.dtb.read_misses 80 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 4211 # DTB read accesses
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system.cpu.dtb.write_hits 2002 # DTB write hits
|
|
system.cpu.dtb.write_misses 47 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 2049 # DTB write accesses
|
|
system.cpu.dtb.data_hits 6133 # DTB hits
|
|
system.cpu.dtb.data_misses 127 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 6260 # DTB accesses
|
|
system.cpu.itb.fetch_hits 3841 # ITB hits
|
|
system.cpu.itb.fetch_misses 50 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 3891 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload0.num_syscalls 17 # Number of system calls
|
|
system.cpu.workload1.num_syscalls 17 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 51215 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 758 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 28344 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 4896 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 1988 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 10026 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.CacheLines 3841 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 26635 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.064164 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.464308 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 21569 80.98% 80.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 505 1.90% 82.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 398 1.49% 84.37% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 435 1.63% 86.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 472 1.77% 87.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 332 1.25% 89.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 468 1.76% 90.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 266 1.00% 91.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 2190 8.22% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 26635 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.095597 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.553432 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 36561 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 11106 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 3971 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 513 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 726 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 381 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 147 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 24763 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 394 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 726 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 36906 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 4191 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 1623 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 4148 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 5283 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 23783 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 282 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 4456 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 17841 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 29807 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 29789 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 8687 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 57 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 1771 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2529 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
|
|
system.cpu.memDep1.insertedLoads 1973 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep1.insertedStores 1111 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
|
|
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 21942 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 9221 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 4863 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 26635 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.724460 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.451046 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 19310 72.50% 72.50% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 2394 8.99% 81.49% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 1620 6.08% 87.57% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 1274 4.78% 92.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1030 3.87% 96.22% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 532 2.00% 98.22% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 319 1.20% 99.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 102 0.38% 99.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 54 0.20% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 26635 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 28 9.18% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 201 65.90% 75.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 76 24.92% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 6749 65.93% 65.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2387 23.32% 89.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1095 10.70% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 10236 # Type of FU issued
|
|
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntAlu 6020 66.45% 66.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemRead 2019 22.28% 88.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemWrite 1016 11.21% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::total 9060 # Type of FU issued
|
|
system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.rate 0.376765 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt::0 157 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::total 305 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate::0 0.008136 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::total 0.015806 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 65537 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 31224 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 17544 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 19575 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1344 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 388 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 261 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread1.forwLoads 45 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.squashedLoads 788 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread1.memOrderViolation 12 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread1.squashedStores 246 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread1.cacheBlocked 288 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 2949 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 377 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 22125 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 143 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 4502 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2364 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 340 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 130 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 639 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 769 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 18625 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts::0 2260 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 1960 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 4220 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 671 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop::0 66 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::1 67 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::total 133 # number of nop insts executed
|
|
system.cpu.iew.exec_refs::0 3318 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::1 2963 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches::0 1546 # Number of branches executed
|
|
system.cpu.iew.exec_branches::1 1419 # Number of branches executed
|
|
system.cpu.iew.exec_branches::total 2965 # Number of branches executed
|
|
system.cpu.iew.exec_stores::0 1058 # Number of stores executed
|
|
system.cpu.iew.exec_stores::1 1003 # Number of stores executed
|
|
system.cpu.iew.exec_stores::total 2061 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.363663 # Inst execution rate
|
|
system.cpu.iew.wb_sent::0 9379 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::1 8440 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::total 17819 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::1 8351 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::total 17564 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers::0 4854 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::1 4443 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::total 9297 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers::0 6502 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::1 5954 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::total 12456 # num instructions consuming a value
|
|
system.cpu.iew.wb_rate::0 0.179889 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::1 0.163058 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::total 0.342946 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout::0 0.746540 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::1 0.746221 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::total 0.746387 # average fanout of values written-back
|
|
system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 647 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 26599 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.481371 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.387327 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 21475 80.74% 80.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 2692 10.12% 90.86% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 910 3.42% 94.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 379 1.42% 95.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 247 0.93% 96.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 153 0.58% 97.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 207 0.78% 97.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 128 0.48% 98.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 408 1.53% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 26599 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
|
|
system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs::0 2050 # Number of memory references committed
|
|
system.cpu.commit.refs::1 2050 # Number of memory references committed
|
|
system.cpu.commit.refs::total 4100 # Number of memory references committed
|
|
system.cpu.commit.loads::0 1185 # Number of loads committed
|
|
system.cpu.commit.loads::1 1185 # Number of loads committed
|
|
system.cpu.commit.loads::total 2370 # Number of loads committed
|
|
system.cpu.commit.membars::0 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::1 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::total 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches::0 1056 # Number of branches committed
|
|
system.cpu.commit.branches::1 1056 # Number of branches committed
|
|
system.cpu.commit.branches::total 2112 # Number of branches committed
|
|
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
|
|
system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
|
|
system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 408 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 113983 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 45899 # The number of ROB writes
|
|
system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 24580 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
|
|
system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
|
|
system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
|
|
system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi::0 8.021143 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi::1 8.021143 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 4.010572 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc::0 0.124671 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.124671 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.249341 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 23552 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 13174 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements::0 0 # number of replacements
|
|
system.cpu.dcache.tags.replacements::1 0 # number of replacements
|
|
system.cpu.dcache.tags.replacements::total 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 214.351374 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 4238 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 341 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 12.428152 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 214.351374 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.052332 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.052332 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.083252 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 10843 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 10843 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3221 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 3221 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1017 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1017 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 4238 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 4238 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 4238 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 4238 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 300 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 300 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 713 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 713 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1013 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1013 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1013 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1013 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25278500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 25278500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 49654940 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 49654940 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 74933440 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 74933440 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 74933440 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 74933440 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3521 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3521 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 5251 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 5251 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 5251 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 5251 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085203 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.085203 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412139 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.412139 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.192916 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.192916 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.192916 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.192916 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 84261.666667 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 84261.666667 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69642.272090 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 69642.272090 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 73971.806515 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 73971.806515 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 6514 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.547445 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 197 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 342 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18892500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 18892500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12000985 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12000985 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30893485 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 30893485 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30893485 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 30893485 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055950 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055950 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.065130 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.065130 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95901.015228 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95901.015228 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82765.413793 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82765.413793 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements::0 7 # number of replacements
|
|
system.cpu.icache.tags.replacements::1 0 # number of replacements
|
|
system.cpu.icache.tags.replacements::total 7 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 314.192674 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 2931 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 627 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 4.674641 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 314.192674 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.153414 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.153414 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 8297 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 8297 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 2931 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 2931 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 2931 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 2931 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 2931 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 2931 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 904 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 904 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 904 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 904 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 904 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 904 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 70022492 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 70022492 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 70022492 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 70022492 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 70022492 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 70022492 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 3835 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 3835 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 3835 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 3835 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 3835 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 3835 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235724 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.235724 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.235724 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.235724 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.235724 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.235724 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77458.508850 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 77458.508850 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 77458.508850 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 77458.508850 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 3069 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 61 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 50.311475 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 7 # number of writebacks
|
|
system.cpu.icache.writebacks::total 7 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 277 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 277 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 277 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 277 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 277 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52227494 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 52227494 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52227494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 52227494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52227494 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 52227494 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163494 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.163494 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.163494 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83297.438596 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83297.438596 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 529.119750 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 965 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.010363 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 314.628551 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 214.491199 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009602 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006546 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.016147 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 319 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029449 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 8773 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 8773 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 624 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 624 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 197 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 197 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 342 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 966 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 342 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 966 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11774500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 11774500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 51248500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 51248500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18588500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 18588500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 51248500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 30363000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 81611500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 51248500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 30363000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 81611500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 627 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 627 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 197 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 197 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 627 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 342 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 969 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 342 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 969 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995215 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995215 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995215 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.996904 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995215 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.996904 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81203.448276 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81203.448276 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82129.006410 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82129.006410 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94357.868020 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94357.868020 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 84483.954451 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 84483.954451 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 624 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 624 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 197 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 197 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10324500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10324500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 45008500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 45008500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16628500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16628500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45008500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26953000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 71961500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45008500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26953000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 71961500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995215 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.996904 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.996904 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71203.448276 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71203.448276 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72129.006410 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72129.006410 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84408.629442 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84408.629442 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 976 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 823 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 627 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 197 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1261 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1944 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21824 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 969 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.002064 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 967 99.79% 99.79% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 969 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
|
|
system.membus.snoop_filter.tot_requests 966 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 820 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 145 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 145 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 821 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1931 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1931 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61760 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 61760 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 966 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 966 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 966 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 1177000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 4.6 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 5133750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 20.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|