a8fbc4ec76
arch/sparc/isa/decoder.isa:
Made sure if a register was assigned to along some control path, then all paths on which no exception would block commit set a value as well. Also, Rs1 is treated as signed for bpr instructions.
arch/sparc/isa/formats/integerop.isa:
Added an IntOpImm11 class which sign extends the SIMM11 immediate field.
arch/sparc/isa/formats/mem.isa:
Fixed how offsets are used, and how disassembly is generated.
arch/sparc/linux/process.cc:
Added fstat and exit_group syscalls.
--HG--
extra : convert_revision : 3b4427d239d254a92179a4137441125b8a364264
695 lines
28 KiB
Text
695 lines
28 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// The actual decoder specification
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//
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decode OP default Unknown::unknown()
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{
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0x0: decode OP2
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{
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//Throw an illegal instruction acception
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0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
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0x1: decode BPCC
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{
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format Branch19
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{
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0x0: bpcci({{
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if(passesCondition(CcrIcc, COND2))
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x2: bpccx({{
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if(passesCondition(CcrXcc, COND2))
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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}
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}
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0x2: Branch22::bicc({{
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if(passesCondition(CcrIcc, COND2))
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x3: decode RCOND2
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{
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format BranchSplit
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{
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0x1: bpreq({{
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if(Rs1.sdw == 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x2: bprle({{
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if(Rs1.sdw <= 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x3: bprl({{
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if(Rs1.sdw < 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x5: bprne({{
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if(Rs1.sdw != 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x6: bprg({{
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if(Rs1.sdw > 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x7: bprge({{
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if(Rs1.sdw >= 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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}
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}
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//SETHI (or NOP if rd == 0 and imm == 0)
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0x4: SetHi::sethi({{Rd = imm;}});
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0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
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0x6: Trap::fbfcc({{fault = new FpDisabled;}});
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}
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0x1: Branch30::call({{
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R15 = xc->readPC();
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NNPC = R15 + disp;
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}});
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0x2: decode OP3 {
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format IntOp {
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0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
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0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
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0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
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0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
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0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
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0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
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0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
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0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
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0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}});
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0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
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0x0A: umul({{
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Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
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YValue = Rd<63:32>;
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}});
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0x0B: smul({{
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Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
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YValue = Rd.sdw;
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}});
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0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}});
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0x0D: udivx({{
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if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
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else Rd.udw = Rs1.udw / Rs2_or_imm13;
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}});
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0x0E: udiv({{
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if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
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else
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{
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Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
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if(Rd.udw >> 32 != 0)
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Rd.udw = 0xFFFFFFFF;
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}
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}});
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0x0F: sdiv({{
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if(Rs2_or_imm13 == 0)
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fault = new DivisionByZero;
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else
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{
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Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13;
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if(Rd.udw<63:31> != 0)
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Rd.udw = 0x7FFFFFFF;
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else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
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Rd.udw = 0xFFFFFFFF80000000ULL;
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}
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}});
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}
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format IntOpCc {
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0x10: addcc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;}},
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{{(Rs1<31:0> + val2<31:0>)<32:>}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
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0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
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0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
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0x14: subcc({{
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int64_t val2 = Rs2_or_imm13;
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Rd = Rs1 - val2;}},
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{{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
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{{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
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{{(~(Rs1<63:1> + (~val2)<63:1> +
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(Rs1 | ~val2)<0:>))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
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);
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0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
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0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
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0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
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0x18: addccc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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int64_t carryin = CcrIccC;
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Rd = resTemp = Rs1 + val2 + carryin;}},
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{{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{(Rs1<63:1> + val2<63:1> +
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((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x1A: umulcc({{
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uint64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;}},
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{{0}},{{0}},{{0}},{{0}});
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0x1B: smulcc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;}},
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{{0}},{{0}},{{0}},{{0}});
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0x1C: subccc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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int64_t carryin = CcrIccC;
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Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
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{{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);
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0x1D: udivxcc({{
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if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
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else Rd = Rs1.udw / Rs2_or_imm13;}}
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,{{0}},{{0}},{{0}},{{0}});
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0x1E: udivcc({{
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uint32_t resTemp, val2 = Rs2_or_imm13;
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int32_t overflow;
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if(val2 == 0) fault = new DivisionByZero;
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else
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{
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resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
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overflow = (resTemp<63:32> != 0);
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if(overflow) Rd = resTemp = 0xFFFFFFFF;
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else Rd = resTemp;
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} }},
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{{0}},
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{{overflow}},
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{{0}},
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{{0}}
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);
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0x1F: sdivcc({{
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int32_t resTemp, val2 = Rs2_or_imm13;
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int32_t overflow, underflow;
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if(val2 == 0) fault = new DivisionByZero;
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else
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{
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Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
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overflow = (resTemp<63:31> != 0);
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underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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if(overflow) Rd = resTemp = 0x7FFFFFFF;
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else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL;
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else Rd = resTemp;
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} }},
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{{0}},
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{{overflow || underflow}},
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{{0}},
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{{0}}
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);
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0x20: taddcc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x21: tsubcc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
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{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x22: taddcctv({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
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if(overflow) fault = new TagOverflow;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x23: tsubcctv({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
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if(overflow) fault = new TagOverflow;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x24: mulscc({{
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int64_t resTemp, multiplicand = Rs2_or_imm13;
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int32_t multiplier = Rs1<31:0>;
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int32_t savedLSB = Rs1<0:>;
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multiplier = multiplier<31:1> |
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((CcrIccN
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^ CcrIccV) << 32);
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if(!YValue<0:>)
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multiplicand = 0;
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Rd = resTemp = multiplicand + multiplier;
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YValue = YValue<31:1> | (savedLSB << 31);}},
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{{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
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{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
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{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
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{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
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);
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}
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format IntOp
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{
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0x25: decode X {
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0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
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0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
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}
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0x26: decode X {
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0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
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0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
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}
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0x27: decode X {
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0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
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0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
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}
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0x28: decode RS1 {
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0x0: rdy({{Rd = YValue;}});
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0x2: rdccr({{Rd = Ccr;}});
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0x3: rdasi({{Rd = Asi;}});
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0x4: PrivTick::rdtick({{Rd = Tick;}});
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0x5: rdpc({{Rd = xc->readPC();}});
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0x6: rdfprs({{Rd = Fprs;}});
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0xF: decode I {
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0x0: Nop::membar({{/*Membar isn't needed yet*/}});
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0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
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}
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}
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0x2A: decode RS1 {
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format Priv
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{
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0x0: rdprtpc({{
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Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
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}});
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0x1: rdprtnpc({{
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Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
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}});
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0x2: rdprtstate({{
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Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
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}});
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0x3: rdprtt({{
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Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
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}});
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0x4: rdprtick({{Rd = Tick;}});
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0x5: rdprtba({{Rd = Tba;}});
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0x6: rdprpstate({{Rd = Pstate;}});
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0x7: rdprtl({{Rd = Tl;}});
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0x8: rdprpil({{Rd = Pil;}});
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0x9: rdprcwp({{Rd = Cwp;}});
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0xA: rdprcansave({{Rd = Cansave;}});
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0xB: rdprcanrestore({{Rd = Canrestore;}});
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0xC: rdprcleanwin({{Rd = Cleanwin;}});
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0xD: rdprotherwin({{Rd = Otherwin;}});
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0xE: rdprwstate({{Rd = Wstate;}});
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}
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//The floating point queue isn't implemented right now.
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0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
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0x1F: Priv::rdprver({{Rd = Ver;}});
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}
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0x2B: BasicOperate::flushw({{
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if(NWindows - 2 - Cansave == 0)
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{
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if(Otherwin)
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fault = new SpillNOther(WstateOther);
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else
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fault = new SpillNNormal(WstateNormal);
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}
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}});
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0x2C: decode MOVCC3
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{
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0x0: Trap::movccfcc({{fault = new FpDisabled;}});
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0x1: decode CC
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{
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0x0: movcci({{
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if(passesCondition(CcrIcc, COND4))
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Rd = Rs2_or_imm11;
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else
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Rd = Rd;
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}});
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0x2: movccx({{
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if(passesCondition(CcrXcc, COND4))
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Rd = Rs2_or_imm11;
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else
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Rd = Rd;
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}});
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}
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}
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0x2D: sdivx({{
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if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
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else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
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}});
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0x2E: decode RS1 {
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0x0: IntOp::popc({{
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int64_t count = 0;
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uint64_t temp = Rs2_or_imm13;
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//Count the 1s in the front 4bits until none are left
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uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
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while(temp)
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{
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count += oneBits[temp & 0xF];
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temp = temp >> 4;
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}
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Rd = count;
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}});
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}
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0x2F: decode RCOND3
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{
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0x1: movreq({{Rd = (Rs1 == 0) ? Rs2_or_imm10 : Rd;}});
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0x2: movrle({{Rd = (Rs1 <= 0) ? Rs2_or_imm10 : Rd;}});
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0x3: movrl({{Rd = (Rs1 < 0) ? Rs2_or_imm10 : Rd;}});
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0x5: movrne({{Rd = (Rs1 != 0) ? Rs2_or_imm10 : Rd;}});
|
|
0x6: movrg({{Rd = (Rs1 > 0) ? Rs2_or_imm10 : Rd;}});
|
|
0x7: movrge({{Rd = (Rs1 >= 0) ? Rs2_or_imm10 : Rd;}});
|
|
}
|
|
0x30: decode RD {
|
|
0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
|
|
0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
|
|
0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
|
|
0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
|
|
0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
|
|
}
|
|
0x31: decode FCN {
|
|
0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
|
|
0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
|
|
}
|
|
0x32: decode RD {
|
|
format Priv
|
|
{
|
|
0x0: wrprtpc({{
|
|
xc->setMiscReg(MISCREG_TPC_BASE + Tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x1: wrprtnpc({{
|
|
xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x2: wrprtstate({{
|
|
xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x3: wrprtt({{
|
|
xc->setMiscReg(MISCREG_TT_BASE + Tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
|
|
0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
|
|
0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
|
|
0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
|
|
0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
|
|
0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
|
|
0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
|
|
0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
|
|
0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
|
|
0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
|
|
0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
|
|
}
|
|
}
|
|
0x34: Trap::fpop1({{fault = new FpDisabled;}});
|
|
0x35: Trap::fpop2({{fault = new FpDisabled;}});
|
|
0x38: Branch::jmpl({{
|
|
Addr target = Rs1 + Rs2_or_imm13;
|
|
if(target & 0x3)
|
|
fault = new MemAddressNotAligned;
|
|
else
|
|
{
|
|
Rd = xc->readPC();
|
|
NNPC = target;
|
|
}
|
|
}});
|
|
0x39: Branch::return({{
|
|
//If both MemAddressNotAligned and
|
|
//a fill trap happen, it's not clear
|
|
//which one should be returned.
|
|
Addr target = Rs1 + Rs2_or_imm13;
|
|
if(target & 0x3)
|
|
fault = new MemAddressNotAligned;
|
|
else
|
|
NNPC = target;
|
|
if(fault == NoFault)
|
|
{
|
|
//CWP should be set directly so that it always happens
|
|
//Also, this will allow writing to the new window and
|
|
//reading from the old one
|
|
Cwp = (Cwp - 1 + NWindows) % NWindows;
|
|
if(Canrestore == 0)
|
|
{
|
|
if(Otherwin)
|
|
fault = new FillNOther(WstateOther);
|
|
else
|
|
fault = new FillNNormal(WstateNormal);
|
|
}
|
|
else
|
|
{
|
|
Rd = Rs1 + Rs2_or_imm13;
|
|
Cansave = Cansave + 1;
|
|
Canrestore = Canrestore - 1;
|
|
}
|
|
//This is here to make sure the CWP is written
|
|
//no matter what. This ensures that the results
|
|
//are written in the new window as well.
|
|
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
|
|
}
|
|
}});
|
|
0x3A: decode CC
|
|
{
|
|
0x0: Trap::tcci({{
|
|
if(passesCondition(CcrIcc, COND2))
|
|
{
|
|
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
|
|
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
|
|
#if FULL_SYSTEM
|
|
fault = new TrapInstruction(lTrapNum);
|
|
#else
|
|
DPRINTF(Sparc, "The syscall number is %d\n", R1);
|
|
xc->syscall(R1);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
DPRINTF(Sparc, "Didn't fire on %s\n", CondTestAbbrev[machInst<25:28>]);
|
|
}
|
|
}});
|
|
0x2: Trap::tccx({{
|
|
if(passesCondition(CcrXcc, COND2))
|
|
{
|
|
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
|
|
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
|
|
#if FULL_SYSTEM
|
|
fault = new TrapInstruction(lTrapNum);
|
|
#else
|
|
DPRINTF(Sparc, "The syscall number is %d\n", R1);
|
|
xc->syscall(R1);
|
|
#endif
|
|
}
|
|
}});
|
|
}
|
|
0x3B: Nop::flush({{/*Instruction memory flush*/}});
|
|
0x3C: save({{
|
|
//CWP should be set directly so that it always happens
|
|
//Also, this will allow writing to the new window and
|
|
//reading from the old one
|
|
if(Cansave == 0)
|
|
{
|
|
if(Otherwin)
|
|
fault = new SpillNOther(WstateOther);
|
|
else
|
|
fault = new SpillNNormal(WstateNormal);
|
|
Cwp = (Cwp + 2) % NWindows;
|
|
}
|
|
else if(Cleanwin - Canrestore == 0)
|
|
{
|
|
Cwp = (Cwp + 1) % NWindows;
|
|
fault = new CleanWindow;
|
|
}
|
|
else
|
|
{
|
|
Cwp = (Cwp + 1) % NWindows;
|
|
Rd = Rs1 + Rs2_or_imm13;
|
|
Cansave = Cansave - 1;
|
|
Canrestore = Canrestore + 1;
|
|
}
|
|
//This is here to make sure the CWP is written
|
|
//no matter what. This ensures that the results
|
|
//are written in the new window as well.
|
|
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
|
|
}});
|
|
0x3D: restore({{
|
|
//CWP should be set directly so that it always happens
|
|
//Also, this will allow writing to the new window and
|
|
//reading from the old one
|
|
Cwp = (Cwp - 1 + NWindows) % NWindows;
|
|
if(Canrestore == 0)
|
|
{
|
|
if(Otherwin)
|
|
fault = new FillNOther(WstateOther);
|
|
else
|
|
fault = new FillNNormal(WstateNormal);
|
|
}
|
|
else
|
|
{
|
|
Rd = Rs1 + Rs2_or_imm13;
|
|
Cansave = Cansave + 1;
|
|
Canrestore = Canrestore - 1;
|
|
}
|
|
//This is here to make sure the CWP is written
|
|
//no matter what. This ensures that the results
|
|
//are written in the new window as well.
|
|
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
|
|
}});
|
|
0x3E: decode FCN {
|
|
0x0: Priv::done({{
|
|
if(Tl == 0)
|
|
return new IllegalInstruction;
|
|
Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
|
|
Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
|
|
Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
|
|
Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
|
|
NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
|
|
NNPC = NPC + 4;
|
|
Tl = Tl - 1;
|
|
}});
|
|
0x1: BasicOperate::retry({{
|
|
if(Tl == 0)
|
|
return new IllegalInstruction;
|
|
Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
|
|
Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
|
|
Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
|
|
Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
|
|
NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
|
|
NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
|
|
Tl = Tl - 1;
|
|
}});
|
|
}
|
|
}
|
|
}
|
|
0x3: decode OP3 {
|
|
format Load {
|
|
0x00: lduw({{Rd = Mem;}}, {{32}});
|
|
0x01: ldub({{Rd = Mem;}}, {{8}});
|
|
0x02: lduh({{Rd = Mem;}}, {{16}});
|
|
0x03: ldd({{
|
|
uint64_t val = Mem;
|
|
RdLow = val<31:0>;
|
|
RdHigh = val<63:32>;
|
|
}}, {{64}});
|
|
}
|
|
format Store {
|
|
0x04: stw({{Mem = Rd.sw;}}, {{32}});
|
|
0x05: stb({{Mem = Rd.sb;}}, {{8}});
|
|
0x06: sth({{Mem = Rd.shw;}}, {{16}});
|
|
0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
|
|
}
|
|
format Load {
|
|
0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
|
|
0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
|
|
0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
|
|
0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
|
|
0x0D: ldstub({{
|
|
Rd = Mem;
|
|
Mem = 0xFF;
|
|
}}, {{8}});
|
|
}
|
|
0x0E: Store::stx({{Mem = Rd}}, {{64}});
|
|
0x0F: LoadStore::swap({{
|
|
uint32_t temp = Rd;
|
|
Rd = Mem;
|
|
Mem = temp;
|
|
}}, {{32}});
|
|
format Load {
|
|
0x10: lduwa({{Rd = Mem;}}, {{32}});
|
|
0x11: lduba({{Rd = Mem;}}, {{8}});
|
|
0x12: lduha({{Rd = Mem;}}, {{16}});
|
|
0x13: ldda({{
|
|
uint64_t val = Mem;
|
|
RdLow = val<31:0>;
|
|
RdHigh = val<63:32>;
|
|
}}, {{64}});
|
|
}
|
|
format Store {
|
|
0x14: stwa({{Mem = Rd;}}, {{32}});
|
|
0x15: stba({{Mem = Rd;}}, {{8}});
|
|
0x16: stha({{Mem = Rd;}}, {{16}});
|
|
0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
|
|
}
|
|
format Load {
|
|
0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
|
|
0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
|
|
0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
|
|
0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
|
|
}
|
|
0x1D: LoadStore::ldstuba({{
|
|
Rd = Mem;
|
|
Mem = 0xFF;
|
|
}}, {{8}});
|
|
0x1E: Store::stxa({{Mem = Rd}}, {{64}});
|
|
0x1F: LoadStore::swapa({{
|
|
uint32_t temp = Rd;
|
|
Rd = Mem;
|
|
Mem = temp;
|
|
}}, {{32}});
|
|
format Trap {
|
|
0x20: ldf({{fault = new FpDisabled;}});
|
|
0x21: decode X {
|
|
0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
|
|
0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
|
|
}
|
|
0x22: ldqf({{fault = new FpDisabled;}});
|
|
0x23: lddf({{fault = new FpDisabled;}});
|
|
0x24: stf({{fault = new FpDisabled;}});
|
|
0x25: decode X {
|
|
0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
|
|
0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
|
|
}
|
|
0x26: stqf({{fault = new FpDisabled;}});
|
|
0x27: stdf({{fault = new FpDisabled;}});
|
|
0x2D: Nop::prefetch({{ }});
|
|
0x30: ldfa({{return new FpDisabled;}});
|
|
0x32: ldqfa({{fault = new FpDisabled;}});
|
|
0x33: lddfa({{fault = new FpDisabled;}});
|
|
0x34: stfa({{fault = new FpDisabled;}});
|
|
0x35: stqfa({{fault = new FpDisabled;}});
|
|
0x36: stdfa({{fault = new FpDisabled;}});
|
|
0x3C: Cas::casa({{
|
|
uint64_t val = Mem.uw;
|
|
if(Rs2.uw == val)
|
|
Mem.uw = Rd.uw;
|
|
Rd.uw = val;
|
|
}});
|
|
0x3D: Nop::prefetcha({{ }});
|
|
0x3E: Cas::casxa({{
|
|
uint64_t val = Mem.udw;
|
|
if(Rs2 == val)
|
|
Mem.udw = Rd;
|
|
Rd = val;
|
|
}});
|
|
}
|
|
}
|
|
}
|