54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
793 lines
88 KiB
Text
793 lines
88 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000015 # Number of seconds simulated
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sim_ticks 14818500 # Number of ticks simulated
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final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 71701 # Simulator instruction rate (inst/s)
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host_op_rate 71694 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 83350191 # Simulator tick rate (ticks/s)
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host_mem_usage 220256 # Number of bytes of host memory used
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host_seconds 0.18 # Real time elapsed on the host
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sim_insts 12745 # Number of instructions simulated
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sim_ops 12745 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62720 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 980 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2699328542 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1533218612 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4232547154 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2699328542 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2699328542 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2699328542 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1533218612 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4232547154 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 4173 # DTB read hits
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system.cpu.dtb.read_misses 101 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 4274 # DTB read accesses
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system.cpu.dtb.write_hits 2094 # DTB write hits
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system.cpu.dtb.write_misses 67 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 2161 # DTB write accesses
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system.cpu.dtb.data_hits 6267 # DTB hits
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system.cpu.dtb.data_misses 168 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 6435 # DTB accesses
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system.cpu.itb.fetch_hits 5272 # ITB hits
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system.cpu.itb.fetch_misses 65 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 5337 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload0.num_syscalls 17 # Number of system calls
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system.cpu.workload1.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 29638 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 6610 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 3711 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1792 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 4939 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 751 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 944 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 1602 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 36672 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 6610 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 1695 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 6124 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 5272 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 768 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 24286 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.510006 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.874831 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 18162 74.78% 74.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 487 2.01% 76.79% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 349 1.44% 78.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 481 1.98% 80.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 433 1.78% 81.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 367 1.51% 83.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 502 2.07% 85.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 575 2.37% 87.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2930 12.06% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 24286 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.223024 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.237330 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 34845 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 5279 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 5199 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 2549 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 678 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 456 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 31855 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 699 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 2549 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 35545 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2460 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 852 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 4962 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 2034 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 29496 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
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system.cpu.rename.LSQFullEvents 2078 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 22198 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 36809 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 36775 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 13058 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 5621 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2720 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
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system.cpu.memDep1.insertedLoads 2704 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep1.insertedStores 1337 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads.
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system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 26000 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 21936 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 12217 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 6791 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 24286 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.903236 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.464516 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 15163 62.44% 62.44% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 3175 13.07% 75.51% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 2422 9.97% 85.48% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 1558 6.42% 91.90% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 1052 4.33% 96.23% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 575 2.37% 98.60% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 252 1.04% 99.63% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 64 0.26% 99.90% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 25 0.10% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 24286 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 11 6.15% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 105 58.66% 64.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 63 35.20% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 7498 68.11% 68.13% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 2352 21.36% 89.52% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 1154 10.48% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 11009 # Type of FU issued
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system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
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system.cpu.iq.FU_type_1::IntAlu 7399 67.71% 67.73% # Type of FU issued
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system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.74% # Type of FU issued
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system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.74% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.76% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemRead 2369 21.68% 89.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemWrite 1154 10.56% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::total 10927 # Type of FU issued
|
|
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntAlu 14897 67.91% 67.93% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntMult 2 0.01% 67.94% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntDiv 0 0.00% 67.94% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatMult 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMult 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShift 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.96% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemRead 4721 21.52% 89.48% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemWrite 2308 10.52% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::total 21936 # Type of FU issued
|
|
system.cpu.iq.rate 0.740131 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::total 179 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate::0 0.004103 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::1 0.004057 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::total 0.008160 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 68413 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 38274 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 19529 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 22089 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1537 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 471 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread1.forwLoads 69 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.squashedLoads 1521 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread1.squashedStores 472 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 2549 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 597 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 26207 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 761 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 5424 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2673 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 269 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 1293 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1562 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 20406 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts::0 2135 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 2153 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 4288 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1530 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop::0 78 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::1 77 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::total 155 # number of nop insts executed
|
|
system.cpu.iew.exec_refs::0 3247 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::1 3223 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::total 6470 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches::0 1671 # Number of branches executed
|
|
system.cpu.iew.exec_branches::1 1692 # Number of branches executed
|
|
system.cpu.iew.exec_branches::total 3363 # Number of branches executed
|
|
system.cpu.iew.exec_stores::0 1112 # Number of stores executed
|
|
system.cpu.iew.exec_stores::1 1070 # Number of stores executed
|
|
system.cpu.iew.exec_stores::total 2182 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.688508 # Inst execution rate
|
|
system.cpu.iew.wb_sent::0 9974 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::1 9875 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::total 19849 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count::0 9831 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::1 9718 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::total 19549 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers::0 5093 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::1 5062 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::total 10155 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers::0 6638 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::1 6585 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::total 13223 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate::0 0.331703 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::1 0.327890 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::total 0.659592 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout::0 0.767249 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::1 0.768717 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::total 0.767980 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 13400 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1351 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 24235 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.527295 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.312718 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 18649 76.95% 76.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 2814 11.61% 88.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1163 4.80% 93.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 521 2.15% 95.51% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 359 1.48% 96.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 238 0.98% 97.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 198 0.82% 98.79% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 82 0.34% 99.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 211 0.87% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 24235 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
|
|
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs::0 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::1 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::total 4096 # Number of memory references committed
|
|
system.cpu.commit.loads::0 1183 # Number of loads committed
|
|
system.cpu.commit.loads::1 1183 # Number of loads committed
|
|
system.cpu.commit.loads::total 2366 # Number of loads committed
|
|
system.cpu.commit.membars::0 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::1 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::total 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches::0 1050 # Number of branches committed
|
|
system.cpu.commit.branches::1 1050 # Number of branches committed
|
|
system.cpu.commit.branches::total 2100 # Number of branches committed
|
|
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 119797 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 54926 # The number of ROB writes
|
|
system.cpu.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 5352 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
|
|
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
|
|
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
|
|
system.cpu.cpi::0 4.651287 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi::1 4.650557 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.325461 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc::0 0.214994 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.215028 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.430022 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 25729 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 14801 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
|
system.cpu.icache.replacements::0 6 # number of replacements
|
|
system.cpu.icache.replacements::1 0 # number of replacements
|
|
system.cpu.icache.replacements::total 6 # number of replacements
|
|
system.cpu.icache.tagsinuse 316.337538 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 4394 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 7.007974 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 316.337538 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.154462 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.154462 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 4394 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 4394 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 4394 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 4394 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 4394 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 4394 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 878 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 878 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 878 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 878 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 878 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 878 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 33797000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 33797000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 33797000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 33797000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 33797000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 33797000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5272 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 5272 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 5272 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 5272 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 5272 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 5272 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.166540 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.166540 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.166540 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.166540 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.166540 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.166540 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38493.166287 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 38493.166287 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 38493.166287 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 38493.166287 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 38493.166287 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 38493.166287 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24965000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 24965000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24965000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 24965000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24965000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 24965000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118930 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.118930 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.118930 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39816.586922 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39816.586922 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements::0 0 # number of replacements
|
|
system.cpu.dcache.replacements::1 0 # number of replacements
|
|
system.cpu.dcache.replacements::total 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 217.393335 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 4714 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 354 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 13.316384 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 217.393335 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.053075 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.053075 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3702 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 3702 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 4714 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 4714 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 4714 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 4714 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 344 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 344 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1062 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1062 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1062 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1062 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14235500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 14235500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24441000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 24441000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 38676500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 38676500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 38676500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 38676500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 4046 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 4046 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 5776 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 5776 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 5776 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 5776 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.085022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.183864 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.183864 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.183864 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.183864 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41382.267442 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 41382.267442 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34040.389972 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 34040.389972 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36418.549906 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 36418.549906 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36418.549906 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 36418.549906 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 135 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 135 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 572 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 572 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 707 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 707 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 707 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 707 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 209 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 209 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9702000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9702000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6308500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6308500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16010500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 16010500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16010500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 16010500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051656 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051656 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061461 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.061461 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061461 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.061461 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46421.052632 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46421.052632 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43208.904110 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43208.904110 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45100 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45100 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45100 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45100 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 438.756109 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 833 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002401 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 316.614928 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 122.141181 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.009662 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.003727 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.013390 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 625 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 209 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 834 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 355 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 980 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 355 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 980 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24324000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9480500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 33804500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6160000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6160000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 24324000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 15640500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 39964500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 24324000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 15640500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 39964500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 627 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 209 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 627 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 355 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 982 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 355 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 982 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996810 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997608 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996810 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996810 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38918.400000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45361.244019 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 40532.973621 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42191.780822 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42191.780822 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 49000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4083.333333 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 209 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 980 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22361500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8845500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31207000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5705500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5705500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22361500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14551000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 36912500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22361500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14551000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 36912500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997608 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35778.400000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42322.966507 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37418.465228 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39078.767123 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39078.767123 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|